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november 1997 1/117 r rev. 1.0 ST7285C 8-bit mcu for rds with 48k rom, 3 k ram, adc, two timers, two spis, i 2 c and sci interfaces n 4.5v to 5.5v supply operating range n operates at 8.664mhz oscillator frequency for rds compatibility n fully static operation n -40 cto+85 c maximum operating temperature range n run, wait, slow, halt and ram retention modes n user rom: 48 kbytes n data ram: 3 kbytes, including 128 byte stack n 80 pin plastic package n 62 multifunctional bidirectional i/o lines: programmable interrupt inputs on some i/os 8 analog inputs emi filtering n two 16-bit timers, each featuring: 2 input captures 2 output compares external clock input (on timer a) pwm and pulse generator modes n rds radio data system filter, demodulator and gbs circuits n 8-bit analog-to-digital converter with 8 channel analog multiplexer n digital watchdog n two spi serial peripheral interfaces n sci serial communications interface n full i 2 c multiple master/ slave interface n 2khz beep signal generator n master reset and power-on reset n 8-bit data manipulation n 63 basic instructions n 17 main addressing modes n 8 x 8 unsigned multiply instruction n true bit manipulation n complete development support on pc/dos/ windows tm real-time emulator n full software package (c-compiler, cross- assembler, debugger) pqfp80 1
2/117 table of contents 117 ST7285C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1 general description . . . . . . . ...............................................5 1.1 introduction .........................................................5 1.2 pin description .......................................................6 1.3 memorymap .........................................................10 2 central processing unit .................................................13 2.1 introduction ........................................................13 2.2 cpu registers . . . . . . . . ...............................................13 3 clocks, reset, interrupts & power saving modes ........................15 3.1 clocksystem........................................................15 3.1.1 general description .................................................15 3.1.2 crystal resonator . . . . . . . . ..........................................15 3.1.3 ceramic resonator . . . ..............................................16 3.1.4 external clock . . . . . . . ..............................................16 3.2 miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................17 3.3 resets...............................................................18 3.3.1 introduction . . . . . . . . ...............................................18 3.3.2 external reset . . . . . . . . . . ...........................................18 3.3.3 reset operation . . . . . . . . . . . . . . . .....................................18 3.3.4 power-on reset . . . . . . . . . . . . . . . .....................................18 3.4 watchdog timer system (wdg) . . .....................................19 3.4.1 introduction . . . . . . . . ...............................................19 3.4.2 functional description . . . ............................................19 3.4.3 watchdog register . . . ..............................................19 3.5 interrupts . . . . ......................................................20 3.6 power saving modes .................................................22 3.6.1 slowmode ........................................................22 3.6.2 waitmode ........................................................22 3.6.3 haltmode.........................................................23 4 on-chip peripherals . . . ...................................................24 4.1 i/oports.............................................................24 4.1.1 introduction . . . . . . . . ...............................................24 4.1.2 generic i/o features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................24 4.1.3 i/o port implementation . . . . . . . . . . . . ..................................27 4.2 serial communications interface. . ..................................28 4.2.1 introduction . . . . . . . . ...............................................28 4.2.2 features . . . . . . . . . . . . . . . ...........................................28 4.2.3 serial data format . .................................................28 4.2.4 data reception and transmission . . . ...................................28 4.2.5 receiver muting and wake-up feature . . . . ..............................28 4.2.6 baud rate generation . . . ............................................29 4.2.7 sci register overview . . . ............................................29 4.3 16-bit timer . . . . ......................................................35 4.3.1 introduction . . . . . . . . ...............................................35 4.3.2 counter . . . . ......................................................35
3/117 table of contents 4.3.3 external clock . . . . . . . ..............................................37 4.3.4 input capture . . . ...................................................39 4.3.5 output compare . . . . ...............................................40 4.3.6 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .........................43 4.4 serial peripheral interface . . . . . . . . . . . . . . . . . . . . .....................45 4.4.1 introduction . . . . . . . . ...............................................45 4.4.2 features . . . . . . . . . . . . . . . ...........................................45 4.4.3 functional description . . . ............................................45 4.4.4 signal description . . . . . . . . ..........................................47 4.4.5 master out slave in (mosi) . ..........................................47 4.4.6 master in slave out (miso) . ..........................................47 4.4.7 serial peripheral control register (spcr) ...............................50 4.4.8 serial peripheral status register (spsr) . . . . . ........................ ...51 4.4.9 serial peripheral data i/o register (spdr) . . . . . .........................53 4.4.10single master and multimaster configurations . . . . ........................53 4.5 i2c bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .........................54 4.5.1 introduction . . . . . . . . ...............................................54 4.5.2 general features . . . . ...............................................54 4.5.3 functional description . . . ............................................54 4.5.4 eprom/rom i c compatibility application note. . . . ...............56 4.5.5 register description .................................................57 4.5.6 i2c state machine: . . . ..............................................61 4.6 a/d converter (adc) . .................................................64 4.6.1 introduction . . . . . . . . ...............................................64 4.6.2 functional description . . . ............................................64 4.6.3 register description .................................................65 4.7 rds filter . . . ........................................................66 4.7.1 features . . . . . . . . . . . . . . . ...........................................66 4.7.2 functional description . . . ............................................67 4.8 rds demodulator . . . . . . . . . . . . . . . .....................................68 4.8.1 features . . . . . . . . . . . . . . . ...........................................68 4.8.2 functional description . . . ............................................69 4.9 rdsg.b.s.............................................................72 4.9.1 introduction . . . . . . . . ...............................................72 4.9.2 features . . . . . . . . . . . . . . . ...........................................72 4.9.3 functional description . . . ............................................74 4.9.4 acquisition of group and block synchronization . . . . .......................77 4.9.5 application tips . . . . . . . . . . . . . . . . . . . . . . . . . . . .........................77 4.9.6 block synchronization software . . .....................................77 4.9.7 error correction software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................77 5software ................................................................78 5.1 st7 architecture . . . . . . . . . . . . . . . .....................................78 5.2 st7 addressing modes ...............................................78 5.3 st7 instruction set . .................................................83 6 electrical characteristics . . . . . . . . . . . . ..................................86 6.1 absolute maximum ratings . ..........................................86 6.2 power considerations . . . . ..........................................87
4/117 table of contents 117 6.3 dc electrical characteristics ......................................88 6.4 ac electrical characteristics ......................................89 6.5 controltiming ......................................................89 7 general information . . . . . . . . . . ...........................................96 7.1 package mechanical data . . . . ........................................96 st72e85 st72t85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 1 general description. . . ...................................................98 1.1 introduction ........................................................98 1.2 pin description ......................................................99 1.3 memorymap.........................................................103 1.4 eprom erasure .....................................................105 1.5 eprom/rom i c compatibility application note .......................106 2 electrical characteristics . . . . .........................................107 2.1 absolute maximum ratings . . . . . . ....................................107 2.2 power considerations. . . ...........................................108 2.3 dc electrical characteristics .....................................109 2.4 ac electrical characteristics. . . ...................................110 2.5 controltiming......................................................110 3 general information . . . . . . . . . . ..........................................117 3.1 package mechanical data . . . . .......................................117
5/117 ST7285C 1 general description 1.1 introduction the ST7285C hcmos microcontroller unit is a member of the st7 family of microcontrollers ded- icated to car radio applications with rds capabili- ty. the device is based on an industry-standard 8- bit core and features an enhanced instruction set. the device is normally operated at an 8.664mhz oscillator frequency for rds compatibility but, thanks to the fully static design, operation is possi- ble down to dc, when rds functionality is not re- quired. under software control, theST7285C may be placed in either wait, slow or halt modes, thus reducing power consumption. the enhanced instruction set and addressing modes afford real programming potential. in addition to standard 8- bit data management, the ST7285C features true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. the device includes an on-chip oscillator, cpu, rom, ram, 62 i/o lines and the following on-chip peripherals: analog-to-digital converter (adc), two industry standard spi serial interfaces, a seri- al communications interface, an i 2 c interface, a digital watchdog timer, two independent 16-bit timers, one featuring an external clock input, and both featuring pulse generator capabilities, 2 in- put captures and 2 output compares. rds filter, demodulator and gbs circuitry for car radio appli- cations is also included. note : for this device, sgs-thomson can only receive motorola s19 format for rom codes. figure 1. ST7285C block diagram *on eprom or otp versions only. power on reset pa0 - pa7 pin 65..72 pb0 - pb7 pin 73..80 oscin oscout reset v pp / test osc 8 -bit core alu vr01735p internal clock address and data bus timer a port a port b a/d converter 8 4 spi b port c pc0 - pc7 pin 5..12 spi a port d i 2 c sci 8 ram 3k rds filter,demod,gbs 8 8 8 timer b 4 4 2 pd0 - pd7 pin 13..20 2 port e pe0 - pe7 pin 25..32 8 port f pf0 - pf7 pin 33..40 8 port h port g ph0 - ph5 pin 53..58 6 pg0 - pg7 pin 45..52 8 rom or eprom* 48k watchdog rdscomp mpx rds fil rds ref ars aint v dd v ss v ddp v ssp v dda v ssa 2 2
6/117 ST7285C 1.2 pin description all i/os from port a to port d, as well as ph0, 1 and 2, feature alternate function compatibility. software selectable input pull-ups are available on ports featuring interrupt capability (pc4, pc5, pd4, pd5, pf0-pf3, pg3). vssa vdda mpx rdsref rdsfil rdscomp ph5 ph4 ph3 ph2/rdsdata ph1/rdsclkout ph0/rdsqual pg7 pg6 pg5 pg4 pg3 pg2 pg1 pg0 ars aint vddp vssp vssp vddp oscout oscin pc0/miso_b pc1/mosi_b pc2/sck_b pc3/ss_b pc4/oc2_b pc5/oc1_b pc6/ic2_b pc7/ic1_b pd0/miso_a pd1/mosi_a pd2/sck_a pd3/ss_a pd4 pd5 pd6/scl pd7/sda reset vpp*/test vdd vss 1 2 3 4 5 6 7 8 9 (i10) 10 (i10) 11 12 13 14 15 16 17 (i9) 18 (i9) 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 (i1) 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 29 30 31 32 37 38 39 40 pb7/beep/ clkout pb6/clkext pb5/oc2_a pb4/oc1_a pb3/ic2_a pb2/ic1_a pb1/rdi pb0/tdo pa7/ain7 pa6/ain6 pa5/ain5 pa4/ain4 pa3/ain3 pa2/ain2 pa1/ain1 pa0/ain0 pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 33 34 35 36 *) on eprom/otp versions only (i2)(i2)(i2)(i2)
7/117 ST7285C pin pin name(s) basic function alternate function remarks 1v ssp ground for output buff- ers - this pin is connected to pin 41 2v ddp power supply for out- put buffers this pin is connected to pin 42 3 oscout oscillator output pin. 4 oscin oscillator input pin. 5 pc0/miso_b i/o port pc0 spi b master in/slave out data input/output alternate function or i/o. the i/o configuration is software selectable as triggered input or push pull output. 6 pc1/mosi_b i/o port pc1 spi b master out/ slave in data input/ output 7 pc2/sck_b i/o port pc2 spi b serial clock 8 pc3/ss_b i/o port pc3 spi b slave select 9 pc4/oc2_b i/o port pc4 output compare 2 on timer b alternate function or i/o. software selectable as triggered input, push pull output, or trig- gered interrupt input with pull up (interrupt i10). 10 pc5/oc1_b i/o port pc5 output compare 1 on timer b 11 pc6/ic2_b i/o port pc6 input capture 2 on timer b alternate function or i/o. the i/o configuration is software selectable as triggered input or push pull output. 12 pc7/ic1_b i/o port pc7 input capture 1 on timer b. 13 pd0/miso_a i/o port pd0 spi a master in/slave out data input/output 14 pd1/mosi_a i/o port pd1 spi a master out/ slave in data input/ output 15 pd2/sck_a i/o port pd2 spi a serial clock 16 pd3/ss_a i/o port pd3 spi a slave select 17 pd4 i/o port pd4 - software selectable as triggered input, push pull output, open drain output or triggered in- terrupt input with pull up (interrupt i9). 18 pd5 i/o port pd5 - 19 pd6/scl i/o port pd6 i 2 c serial clock alternate function or i/o. the i/o configuration is software selectable as triggered input or open drain output. 20 pd7/sda i/o port pd7 i 2 c serial data 21 reset general reset - bidirectional. an active low signal forces mcu initialization. this event is the top priority non- maskable interrupt. as an output, it can be used to reset external peripherals. 22 test reserved - input. this pin must be tied directly to v ss during normal operation. 23 v dd power supply for all log- ic circuitry - except for output buffers and pull-ups. 24 v ss ground for all logic cir- cuitry - 25 pe0 i/o port pe0 - software selectable as triggered input or push pull output. 26 pe1 i/o port pe1 - 27 pe2 i/o port pe2 - 28 pe3 i/o port pe3 - 29 pe4 i/o port pe4 - 30 pe5 i/o port pe5 - 31 pe6 i/o port pe6 - 32 pe7 i/o port pe7 -
8/117 ST7285C 33 pf0 i/o port pf0 - software selectable as triggered input, a push pull output, open drain output, or triggered in- terrupt input with pull up (interrupt i2). 34 pf1 i/o port pf1 - 35 pf2 i/o port pf2 - 36 pf3 i/o port pf3 - 37 pf4 i/o port pf4 - software selectable as a triggered input or as a push pull output. 38 pf5 i/o port pf5 - 39 pf6 i/o port pf6 - 40 pf7 i/o port pf7 - 41 v ssp ground for output buff- ers. - this pin is connected to pin 1. 42 v ddp power supply for out- put buffers - this pin is connected to pin 2. 43 aint reserved - must be tied to 5v 44 ars reserved - must be tied to 5v 45 pg0 i/o port pg0 - software selectable as triggered input or push pull output. 46 pg1 i/o port pg1 - 47 pg2 i/o port pg2 - 48 pg3 i/o port pg3 - software selectable as triggered input, a push pull output, open drain output, or triggered in- terrupt input with pull up (interrupt i1). 49 pg4 i/o port pg4 - software selectable as triggered input or push pull output. note that ph0, 1, 2 offer alternate function capabilities for test purposes. 50 pg5 i/o port pg5 - 51 pg6 i/o port pg6 - 52 pg7 i/o port pg7 - 53 ph0/ rdsqual i/o port ph0 rds quality signal 54 ph1/ rdsclkout i/o port ph1 rds gbs clock out signal 55 ph2/ rdsdata i/o port ph2 rds gbs data signal 56 ph3 i/o port ph3 - software selectable as triggered input or high voltage (10v max) open drain output. 57 ph4 i/o port ph4 - 58 ph5 i/o port ph5 - 59 rdscomp rds comp input signal used to feed the demodulator from an external filter when the internal filter is switched off. 60 rdsfil rds filtered output signal used for demodulator test purposes. 61 rdsref rds input reference 62 mpx rds input signal 63 v dda analog power supply for rds and adc circuits 64 v ssa analog ground 65 pa0/ain0 i/o port pa0 analog input to adc alternate function or i/o. the i/o configuration is software selectable as triggered input or push pull output. note that when a pin is used as analog input it must not be configured as an output to avoid conflicts with the analog volt- age to be measured. 66 pa1/ain1 i/o port pa1 67 pa2/ain2 i/o port pa2 68 pa3/ain3 i/o port pa3 69 pa4/ain4 i/o port pa4 70 pa5/ain5 i/o port pa5 71 pa6/ain6 i/o port pa6 72 pa7/ain7 i/o port pa7 pin pin name(s) basic function alternate function remarks
9/117 ST7285C 73 pb0/tdo i/o port pb0 sci transmit data out alternate function or i/o. the i/o configuration is software selectable as triggered input or push pull output. 74 pb1/rdi i/o port pb1 sci receive data in 75 pb2/ic1_a i/o port pb2 input capture 1 on timer a 76 pb3/ic2_a i/o port pb3 input capture 2 on timer a 77 pb4/oc1_a i/o port pb4 output compare 1 on timer a 78 pb5/oc2_a i/o port pb5 output compare 2 on timer a 79 pb6/clkext i/o port pb6 external clock on timer a 80 pb7/beep/ clkout i/o port pb7 beep or cpu clock. this pin can be a push pull output delivering the beep signal (2khz) or the cpu clock, ac- cording to the miscellaneous register settings. pin pin name(s) basic function alternate function remarks
10/117 ST7285C 1.3 memory map table 1. memory map address block register name reset status remarks 0000h 0001h 0002h 0003h port a data reg data direction reg not used not used 00h 00h r/w register r/w register absent absent 0004h 0005h 0006h 0007h port b data reg data direction reg not used not used 00h 00h r/w register r/w register absent absent 0008h 0009h 000ah 000bh port c data reg data direction reg option reg not used 00h 00h --00----b r/w register r/w register r/w register absent 000ch 000dh 000eh 000fh port d data reg data direction reg option reg not used 00h 00h --00----b r/w register r/w register r/w register absent 0010h 0011h 0012h 0013h port e data reg data direction reg not used not used 00h 00h r/w register r/w register absent absent 0014h 0015h 0016h 0017h port f data reg data direction reg option reg not used 00h 00h ----0000b r/w register r/w register r/w register absent 0018h 0019h 001ah 001bh port g data reg data direction reg option reg not used 00h 00h ----0---b r/w register r/w register r/w register absent 001ch 001dh 001eh 001fh port h data reg data direction reg not used not used 00h 00h r/w register r/w register absent absent 0020h miscellaneous reg- ister 00h see register description 0021h 0022h 0023h spi a data i/o reg control reg status reg xxh 0xh 00h r/w register r/w register read only register 0024h wdg watchdog register 7fh see register description 0025h 0026h 0027h spi b data i/o reg control reg status reg xxh 0xh 00h r/w register r/w register read only register
11/117 ST7285C 0028h 0029h 002ah 002bh 002ch 002dh 002eh i 2 c cr: control register sr1: status register 1 sr2: status register 2 ccr: clock control register oar1: own address register 1 oar2: own address register 2 dr: data register 00h 00h 00h 00h 00h 00h 00h r/w register read only register read only register r/w register r/w register r/w register r/w register 002fh 0030h reserved 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh timer a control reg2 control reg1 status reg input capture1 high register input capture1 low register output compare1 high register output compare1 low register counter high register counter low register alternate counter high register alternate counter low register input capture2 high register input capture2 low register output compare2 high register output compare2 low register 00h 00h xxh xxh xxh xxh xxh ffh fch 00h 00h xxh xxh xxh xxh r/w register r/w register read only register read only register read only register r/w register r/w register read only register read only register read only register read only register read only register read only register r/w register r/w register 0040h reserved 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh 004eh 004fh timer b control reg2 control reg1 status reg input capture1 high register input capture1 low register output compare1 high register output compare1 low register counter high register counter low register alternate counter high register alternate counter low register input capture2 high register input capture2 low register output compare2 high register output compare2 low register 00h 00h xxh xxh xxh xxh xxh ffh fch 00h 00h xxh xxh xxh xxh r/w register r/w register read only register read only register read only register r/w register r/w register read only register read only register read only register read only register read only register read only register r/w register r/w register 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h sci sci prescaler scsr: status register scdr: data register scbrr: baud rate register sccr1: control register 1 sccr2: control register 2 pscbrr: receive baud rate reg reserved pscbrt: transmit baud rate reg 1100000xb xxh 00x----xb xxh 00h 00h --- 00h read only register r/w register r/w register r/w register r/w register r/w register reserved st use r/w register 0058h reserved 0059h reserved 005ah 005bh rds filter rds fi1 rds fi2 r/w register r/w register address block register name reset status remarks
12/117 ST7285C 005ch 005dh 005eh 005fh rds demodulator rds de1 rds de2 rds de3 rds de4 see register description 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh 006ch 006dh 006eh 006fh rds gbs sr0 -shift reg 0 sr1 -shift reg 1 sr2 -shift reg 2 sr3 -shift reg 3 sy0 -polynomial reg 0 sy1 -polynomial reg 1 gs_cnt count reg gs_int interrupt reg dr0 -rdsdat reg 0 dr1 -rdsdat reg 1 dr2 -rdsdat reg 2 dr3 -rdsdat reg 3 qr0 -quality reg 0 qr1 -quality reg 1 qr2 -quality reg 2 qr3 -quality reg 3 see register description 0070h 0071h adc data reg control/status reg xxh 00h read only register r/w register 0072h to 007fh reserved 0080h to 0bffh 0c00h to 0c7fh ram 3k bytes of which stack 128 bytes user variables and subroutine nesting 0c80h to 3fffh reserved 4000h to ffdfh rom 48k bytes (49120 bytes) user application code and data ffe0h to ffff h user vectors interrupt and reset vectors address block register name reset status remarks
13/117 ST7285C 2 central processing unit 2.1 introduction the cpu has a full 8-bit architecture. six internal registers allow efficient 8-bit data manipulation. the cpu is capable of executing 63 basic instruc- tions and features 17 main addressing modes. 2.2 cpu registers the 6 cpu registers are shown in the program- ming model in figure 2. following an interrupt, all registers except y are pushed onto the stack in the order shown in figure 3. they are popped from stack in the reverse order. accumulator (a). the accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calcula- tions as well as data manipulations. index registers (x and y). these 8-bit registers are used to create effective addresses or as tem- porary storage areas for data manipulation. the cross-assembler generates a precede instruc- tion (pre) to indicate that the following instruction refers to the y register. the y register is never au- tomatically stacked. interrupt routines must push or pop it by using the push and pop instructions. program counter (pc). the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. figure 2. organization of internal cpu registers accumulator: x index register: y index register: program counter: stack pointer: condition code register: x = undefined reset value: 70 xx xxxxxx reset value: 70 xx xxxxxx reset value: 70 xx xxxxxx 15 70 reset value = device dependent, see memory map reset value: 70 xx xxxxxx 15 70 reset value = device dependent, see memory map
14/117 ST7285C cpu registers (cont'd) stack pointer (sp) the stack pointer is a 16-bit register. since the stack size can vary from device to device, the appropriate number of most signifi- cant bits are forced so as to map the stack as de- fined in the memory map. the number of least sig- nificant digits thus available to the user will depend on the stack size, for example in the case of a 128 byte stack, 7 bits will be available whereas in the case of a 64 byte stack, only 6 bits will be available. the stack is used to save the cpu context during subroutine calls or interrupts. the user may also directly manipulate the stack by means of the push and pop instructions. following an mcu reset, or after a restore fol- lowing a reset stack pointer instruction (rsp), the stack pointer is set to point to the highest loca- tion in the stack. it is then decremented after data has been pushed onto the stack and incremented after data is popped from the stack. when the low- er limit is exceeded, the stack pointer wraps around to the stack upper limit. the previously stored information is then overwritten and there- fore lost. the upper and lower limits of the stack area are shown in the memory map. a subroutine call occupies two locations and an in- terrupt five locations in the stack area. condition code register (cc) the condition code register is a 5-bit register which indicates the result of the instruction just executed as well as the state of the processor. these bits can be individu- ally tested by a program and specified action taken as a result of their state. the following paragraphs describe each bit of the cc register in turn. half carry bit (h) the h bit is set to 1 when a carry occurs between bits 3 and 4 of the alu during an add or adc instruction. the h bit is useful in bcd arithmetic subroutines. interrupt mask (i) when the i bit is set to 1, all in- terrupts except the trap software interrupt are disabled. clearing this bit enables interrupts to be passed to the processor core. interrupts requested while i is set are latched and can be processed when i is cleared (only one interrupt request per in- terrupt enable flag can be latched). negative (n) when set to 1, this bit indicates that the result of the last arithmetic, logical or data ma- nipulation is negative (i.e. the most significant bit is a logic 1). zero (z) when set to 1, this bit indicates that the result of the last arithmetic, logical or data manipu- lation is zero. carry/borrow (c) when set, c indicates that a carry or borrow out of the alu occured during the last arithmetic operation. this bit is also affected during execution of bit test, branch, shift, rotate and store instructions. figure 3. stacking order increasing memory unstack accumulator x index register pch pcl (push) decreasing memory 111 vr000074 0 7 addresses addresses stack (pop) condition code return interrupt
15/117 ST7285C 3 clocks, reset, interrupts & power saving modes 3.1 clock system 3.1.1 general description the mcu accepts either a crystal or ceramic res- onator, or an external clock signal to drive the in- ternal oscillator. the internal clock (cpu clk run- ning at f cpu ) is derived from the external oscillator frequency (f osc ) . the external oscillator clock is first divided by 2, and an additional division factor of 2, 4, 8, or 16 can be applied, in slow mode, to reduce the frequency of the cpu clock (see note 1); this clock signal is also routed to the on- chip peripherals. the cpu clock signal consists of a square wave with a duty cycle of 50%. figure 4. external clock source connections figure 5. equivalent crystal circuit 3.1.2 crystal resonator the internal oscillator is designed to operate with an at-cut parallel resonant quartz crystal resona- tor in the frequency range specified for f osc .the circuit shown in figure 6 is recommended when using a crystal, and table 2 lists the recommend- ed capacitance and feedback resistance values. the crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time. use of an external cmos oscillator is recom- mended when crystals outside the specified fre- quency ranges are to be used. figure 6. crystal/ceramic resonator figure 7. clock prescaler block diagram note 1: additional division factor of cpu clock is only available on l5/l6. osc in osc out extern al clock nc osc in osc out r s l 1 c 1 c 0 osc in osc out c oscin c oscout r p osc in osc out c oscin c oscout r p %2 %2,4,8,16 cpuclk to cpu and peripherals
16/117 ST7285C clock system (cont'd) 3.1.3 ceramic resonator a ceramic resonator may be used as an alterna- tive to a crystal in low-cost applications. the circuit shown in figure 6 is recommended when using a ceramic resonator. table 3 lists the recommended feedback capacitance and resistance values. the manufacturer of the particular ceramic resonator being considered should be consulted for specific information. table 2. recommended values for crystal resonator 3.1.4 external clock an external clock may be applied to the oscin in- put with the oscout pin not connected, as shown on figure 4. the t oxov and t ilch specifications do not apply when using an external clock input. the equivalent specification of the external clock source should be used instead of t oxov or t ilch . see control timing section. table 3.recommended values for ceramic resonator figure 8. timing diagram for internal cpu clock frequency transistions 2mhz 4mhz 8mhz unit r smax 400 75 60 w c 0 5 7 10 pf c 1 81215ff c oscin 15-40 15-30 15-25 pf c oscout 15-30 15-25 15-20 pf r p 10 10 10 m w q 304060 10 3 2-8mhz unit r smax 10 w c 0 40 pf c 1 4.3 pf c oscin 30 pf c oscout 30 pf r p 1-10 m w q 1250 miscellaneous register 00 10 1 10 vr02062b new frequency requested new frequency active when f osc /4 & f osc /8 = 0 normal mode active normal mode requested psm1:psm0 sms f osc /2 f osc /4 f osc /8 f cpu
17/117 ST7285C 3.2 miscellaneous register the miscellaneous register allows one to select the slow operating mode and to set the clock di- vision prescaler factor. bits 3 and 4 allow one to set pb7 functionality (i/o, cpu clock o/p or beep signal o/p), while bits 6 and 7 determine the signal conditions which will trigger an interrupt request on i/o pins having interrupt capability. register address: 0020h e read/ write reset value: 00h b7, b6 - ei1, ei0 : external interrupt option 0 0 - negative edge and low level (reset state) 1 0 - negative edge only 0 1 - positive edge only 1 1 - positive and negative edge this selection applies globally to the four external interrupts: i1, i2, i9 and i10. b6 and b7 can be written only when the interrupt mask (i) of the cc (condition code) register is set to 1. b5 - reserved b4, b3 - sk1, ck0 : clock/beep output 0 0 - i/o port (reset state) 1 0 - i/o port 0 1 - cpu clock output to pin pb7 1 1 - 2khz beep signal output to pin pb7 (at 8.664 mhz oscillator frequency) b2, b1 - sm1,sm0: cpu clock prescaler for slow mode 0 0 - oscillator frequency / 4 1 0 - oscillator frequency / 8 0 1 - oscillator frequency / 16 1 1 - oscillator frequency / 32 b0 - sms: slow mode select 0- normal mode - oscillator frequency / 2 (reset state) 1- slow mode (bits b1 and b2 define the prescaler factor) 70 ei1 ei0 b5 sk1 ck0 sm1 sm0 sms
18/117 ST7285C 3.3 resets 3.3.1 introduction there are four sources of reset: reset pin (external source) power-on reset (internal source) watchdog (internal source) the reset service routine vector is located at ad- dress fffeh-ffffh. 3.3.2 external reset the reset pin is both an input and an open-drain output with integrated pull up resistor. when one of the internal reset sources is active, the reset pin is driven low to reset the whole application. 3.3.3 reset operation the duration of the reset condition, which is also reflected on the output pin, is fixed at 4096 internal cpu clock cycles. a reset signal originating from an external source must have a duration of at least 1.5 internal cpu clock cycles in order to be recog- nised. at the end of the power-on reset cycle, the mcu may be held in the reset condition by an ex- ternal reset signal. the reset pin may thus be used to ensure v dd has risen to a point where the mcu can operate correctly before the user pro- gram is run. following a reset event, or after exit- ing halt mode, a 4096 cpu clock cycle delay pe- riod is initiated in order to allow the oscillator to stabilise and to ensure that recovery has taken place from the reset state. during the reset cycle, the device reset pin acts as an output that is pulsed low for 3 machine cy- cles (6 oscillator cycles). in its high state, an inter- nal pull-up resistor of about 300k w is connected to the reset pin. this resistor can be pulled low by external circuitry to reset the device. 3.3.4 power-on reset this circuit detects the ramping up of v dd ,and generates a pulse that is used to reset the applica- tion (at approximately v dd = 2v). power-on reset is designed exclusively to cope with power-up conditions, and should not be used in order to attempt to detect a drop in the power supply voltage. caution : to re-initialize the power-on reset, the power supply must fall below approximately 0.8v (vtn), prior to rising above 2v. if this condition is not respected, on subsequent power-up the reset pulse may not be generated. an external pulse may be required to correctly reactivate the circuit. figure 9. reset block diagram vdd counter reset to st7 vr2062c 300k watchdog reset or dlpss reset oscillator signal internal reset
19/117 ST7285C 3.4 watchdog timer system (wdg) 3.4.1 introduction the watchdog timer is used to detect the oc- curence of a software fault, usually generated by external interference or by unforeseen logical con- ditions, which causes the application program to abandon its normal sequence. the watchdog cir- cuit generates an mcu reset on expiry of a pro- grammed time period, unless the program refresh- es the counter's contents before it is decremented to zero. 3.4.2 functional description the counter is decremented every 12,288 ma- chine cycles, and the length of the timeout period can be programmed by the user in 64 increments, ranging from 12,288 machine cycles to 786,432 machine cycles, depending on the value loaded in bits 0-5 of the watchdog register. the application program must be written so that the watchdog register is reloaded at regular intervals during nor- mal operation. the watchdog is not activated automatically on reset, and must be activated by the user program if required. once activated it cannot be disabled, save by a reset. during the reset cycle, the device reset pin acts as an output that is pulsed low for 3 machine cy- cles (6 oscillator cycles). in its high state, an inter- nal pull-up resistor of about 100k w is connected to the reset pin. this resistor can be pulled low by external circuitry to reset the device. the watchdog delay time is defined by bits 5-0 of the watchdog register; bit 6 must always be set in order to avoid generating an immediate reset. conversely, this can be used to generate a soft- ware reset (bit 7 = 1, bit 6 = 0). once bit 7 is set, it cannot be cleared by software: i.e. the watchdog cannot be disabled by software without generating a reset. the watchdog timer must be reloaded before bit 6 is decremented to o0o to avoid a reset. following a reset, the watchdog register will contain 7fh (bits 0-6 = 1, bit 7 = 0). if the watchdog is activated, the halt instruction will generate a reset. if the circuit is not used as a watchdog (i.e. bit 7 is never set), bits 6 to 0 may be used as a simple 7- bit tim e r, for instance as a real time clock. since no interrupt will be generated under these conditions, the watchdog register must be monitored by soft- ware. 3.4.3 watchdog register register address: 0024h e read/ write reset value: 0111 1111 (7fh) b7 = wdga: activation bit (is active if set) b6-0 = t6-t0 : 7-bit timer counter (msb to lsb) table 4. watchdog timing (f osc = 8 mhz) 70 wdga t6 t5 t4 t3 t2 t1 t0 wdg register initial value wdg timeout period (ms) ff 197 c0 3
20/117 ST7285C 3.5 interrupts a list of interrupt sources is given intable 5 below, together with relevant details for each source. in- terrupts are serviced according to their order of pri- ority, starting with i0, which has the highest priori- ty, and so to i11, which has the lowest priority. the following list describes the origins for each in- terrupt level: i0 connected to software interrupt (trap) i1 connected to port g3 i2 connected to port f0, f1, f2, f3 i3 connected to spi a i4 connected to timer a i5 connected to gbs interrupt i6 connected to timer b i7 connected to spi b i8 connected to sci i9 connected to ports d4, d5 i10 connected to ports c4, c5 i11 connected to i 2 c exit from halt mode may only be triggered by an external interrupt on one of the following ports: c4(i10), c5(i10), d4(i9), d5(i9), f0(i2), f1(i2), f2(i2), f3(i2) and g3(i1). if more than one input pin of a group connected to the same interrupt line is selected simultaneously, these will be logically ored. table 5. interrupt mapping interrupt source vector address interrupts register flag name cpu interrupts - fffeh-ff ffh reset n/a n/a reset i0 fffch-fffdh software n/a n/a trap i1 fffah-fffbh ext. interrupt (port g3) n/a n/a int1 i2 fff8h-fff 9h ex. interrupt (ports f0, f1, f2, f3) n/a n/a int2 i3 fff6h-fff 7h transfer complete spi a status spif1_a spi_a a a mode fault a modf1_a a i4 fff4h-fff 5h input capture 1 timer a status icf1_a timer_a a a output compare 1 a ocf1_a a a a input capture 2 a icf2_a a a a output compare 2 a ocf2_a a a a timer overflow a tof_a a i5 fff2h-fff 3h rds block interrupt. rds grp vsi cni gbs i6 fff0h-fff 1h input capture 1 timer b status icf1_b timer_b a a output compare 1 a ocf1_b a a a input capture 2 a icf2_b a a a output compare 2 a ocf2_b a a a timer overflow a tof_b a i7 ffeeh-ffefh transfer complete spi b status spif2_b spi_b a a mode fault a modf1_b a i8 ffech-ffedh transmit buffer empty sci status tdre sci a a transmit complete a tc a a a receive buffer full a rdrf a a a idle line detect a idle a a a overrun a or a i9 ffeah-ffe bh ext. interrupt (ports d4,d5) n/a n/a int9 i10 ffe8h-ffe9h ext. interrupt (port c4, c5) n/a n/a int10 i11 ffe6h-ffe7h byte transmission finished i 2 c status btf i2c a a bus error a berr i2c a a stop detection a sstop i2c
21/117 ST7285C interrupts (cont'd) figure 10. interrupt processing flowchart note 1. see table 5 . interrupt mapping from reset trap fetch next instruction of appropriate interrupt service routine execute instruction push pc,x,a,cc set i bit to 1 vr01172b n y load pc with appropriate interrupt vector ( 1) i bit = 1 n y onto stack
22/117 ST7285C 3.6 power saving modes 3.6.1 slow mode the following power saving mode may be select- ed by setting the relevant bits in the miscellaneous register as detailed in section3.2. in slow mode, the oscillator frequency can be di- vided by 4, 8, 16 or 32 rather than by 2. the cpu and peripherals are clocked at this lower frequen- cy, and therefore the rds filter cannot operate correctly in this mode. slow mode is used to re- duce power consumption, and enables the user to adapt clock frequency to available supply voltage. 3.6.2 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. all peripher- als remain active. during wait mode, the i bit (cc register) is cleared, so as to enable all interrupts. all other registers and memory remain un- changed. the mcu will remain in wait mode until an interrupt or reset occurs, whereupon the pro- gram counter branches to the starting address of the interrupt or reset service routine. refer to figure 11 below. figure 11. wait mode flow chart wait wait y vr02062d n y y n external interrupt reset restart processor clock fetch reset vector or service interrupt peripheral interrupt n active oscillator and peripherals clocks active processor clock stopped
23/117 ST7285C power saving modes (cont'd) 3.6.3 halt mode the halt instruction places the mcu in its lowest power consumption mode. in halt mode the in- ternal oscillator is turned off, causing all internal processing to be halted. during halt mode, the i bit in the cc register is cleared so as to enable external interrupts. all other registers and memory remain unaltered and all input/output lines remain unchanged. this state will endure until an external interrupt (i1, i2, i9, i10) or a reset is generated, whereupon the in- ternal oscillator is restarted. a delay of 4096 cpu clock cycles is initiated prior to restarting the appli- cation, in order to allow the oscillator to stabilize. the external interrupt or reset causes the pro- gram counter to be set to the address of the corre- sponding interrupt or reset service routine. figure 12. halt mode flow chart n y vr02062e n external interrupt wait halt y stop oscillator and all clocks clear i-bit reset oscillator in slow mode turn on oscillator wait for 4096 cpu clock time delay fetch reset vector or service interrupt
24/117 ST7285C 4 on-chip peripherals 4.1 i/o ports 4.1.1 introduction each i/o port can contain up to 8 individually pro- grammable i/os. the mcu features seven 8-bit ports (a, b, c,... g) and one 6-bit-port (h). each i/ o pin is dedicated to its main functionality, thus re- ducing and simplifying its programmability. the current chapter describes the generic i/o structure used in the mcu. all i/os are based on a generic circuit, of which a block diagram is given in figure 13. in most cases the functions are simplified, and several sub- blocks may be missing (such as, for instance, the analog switch on ports b to h or pull-up and inter- rupt logic for most of the i/o ports). some registers may also be absent where their functionality is re- dundant: it is therefore advisable to consult the memory map in section1.3 and the pin description in section 1.2 for proper use of any particular i/o. only ports c4, c5, d4, d5, f0, f1, f2, f3, g3 fea- ture interrupt capability. the following sub-section 4.1.2 contains generic information on st7 i/o ports. for information spe- cific to this device, please refer to sub-section 4.1.3. 4.1.2 generic i/o features the i/o ports offer the following generic features: inputs with schmitt trigger analog inputs, when connected via internal mul- tiplexer interrupt generation, maskable by software emi compliance thanks to reduced noise radia- tion due to lowered cross-current in push pull mode and reduced input susceptibility. this fea- ture is particularly relevant in rds applications. each generic i/o pin may be individually program- mable by software as: input: no pull-up, no interrupt generation input: pull-up, no interrupt generation input: pull-up, interrupt generation input: pull-down, no interrupt generation output: push-pull output: open-drain, no pull-up output: open-drain, with pull-up 4.1.2.1 port registers each port may be associated with up to four regis- ters: data register (dr) address 0000 0000 000x xx00b; always present. data direction register (ddr) address 0000 0000 000x xx01b; always present. option register (or) address 0000 0000 000x xx10b; depending on i/o dedication. pull-up register (pur) address 0000 0000 000x xx11b; depending on i/o dedication. these are not internal cpu registers and must be accessed by reading and writing to the relevant memory locations. refer totable 1 - memory map for the respective addresses and reset values. 4.1.2.2 functional description each i/o pin may be programmed independently as an analog input if the port features analog capa- bilities, as a digital input or a digital output with var- ious variants, using the corresponding register bits. when programmed as a digital input, a pull-up or a pull-down resistor can, if present, be activated by software. only when enabling the pull-up, can an interrupt function be programmed by software. when programmed as an output, the i/o pin can be programmed to operate either in push-pull or in open-drain mode. the interrupts generated by a port (active low) are aoredo to a single interrupt line that can be routed to a cpu interrupt.
25/117 ST7285C i/o ports (cont'd) figure 13. generic i/o circuitry v dd pad from other bits dr sel or sel ddr sel pur sel pur ddr or dr data bus interrupt m u x signal from alternate trigger enable pad_trig analog switch analog enable common analog rail from adc m u x alternate function enable configuration decoder alternate function enable configuration decoder function
26/117 ST7285C i/o ports (cont'd) 4.1.2.3 operating modes all i/o pins may be configured as inputs or outputs by programming the corresponding bits of the dr, ddr, or and pur memory-mapped registers. table 6 illustrates the available operating modes. during reset, dr, ddr, or and pur are initial- ized to a low level. table 6. i/o operating modes note: (1) this state can add static current consumption. input mode in input mode, both the analog multiplexer and the port buffer are switched to a high impedance state. to avoid ringing with slowly rising or falling input signals and to increase noise immunity, the inputs are equipped with schmitt-triggers. the state of the pin is readable through the data register. the pin state is read directly from the schmitt trigger's output and not from the data register. there are four different input modes, as illustrated in table 6. note : pull-up and pull-down devices are not imple- mented by means of linear resistors, but by means of resistive transistors. interrupt function the interrupt signals of all activated bits are nanded together, so that whenever at least one of the activated inputs goes low, the port's com- mon interrupt output will go high in order to acti- vate the cpu interrupt input. output mode in output mode, the port output buffer is activated and drives the output according to the content of the data register, dr. in this mode, the analog multiplexer, when present, is switched to high im- pedance and the interrupt is disabled. data written to the dr is directly copied to the out- put pins. a read operation of dr will be directly performed from the dr register, so that the output data stored in dr is readable, regardless of the logic levels at the output pin due to output loading. there are three different output modes for the standard i/o pins as illustrated intable 6. alternate function alternate functions take priority over standard i/o programming; if a peripheral needs to use a pad, the alternate function is automatically activated. the signal from the peripheral is output to the pad (automatically configured in this case in push-pull or open drain modes without pull-up and pull- down), and controlled directly by the peripheral. the signal to be input to the peripheral from the pad is taken after the schmitt trigger and is control- led directly by the peripheral. in this case, the pin's state is readable as in input mode by addressing the data register and by configuring the pad in input mode (ddr=0). analog input mode in analog input mode (activated by the adc), the analog multiplexer is activated and switches the analog voltage present on the selected pin (pins pa0 to pa7) to the common analog rail. the com- mon analog rail is connected to the analog to dig- ital converter (see section 4.6) input. it is not rec- ommended to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is not recommended to have clock- ing pins located close to a selected analog pad. warning : before activating the analog input mode, the i/o state must be set to: input, no pull-up, no interrupt (ddr = 0, or = 0, pur = 1) the alternate function must not be activated as long as the pad is configured as input with inter- rupt, in order to avoid generating spurious inter- rupts. analog input mode is only implemented for pins pa0 to pa7. the analog input voltage level must be within the limits stated in the absolute maxi- mum ratings. ddr or pur mode option 0 0 0 input pull-up, no interrupt 0 0 1 input no pull-up, no interrupt 0 1 0 input pull-up, interrupt 0 1 1 input pull-down, no interrupt 1 0 0 output open-drain, pull-up 1 0 1 output open-drain, no pull-up 1 1 0 output reserved (1) 1 1 1 output push-pull, no pull-up, no pull-down
27/117 ST7285C i/o ports (cont'd) 4.1.3 i/o port implementation on the ST7285C, the pull down is always absent, the pull up exists only where an interrupt facility is present (ports c4, c5, d4, d5, f0, f1, f2, f3, g3). on port a, the analog inputs are directly con- trolled by the adc.the i/o port register configura- tions are reduced to the following. 4.1.3.1 ports a0-a7, b0-b7, c0-c3, c6, c7, d0- d3, d6, d7,e0-e7, f4-f7, g0-g2, g4-g7, h0-h5 these ports do not offer interrupt capabilities. note: open drain i/o is implemented on i2c pins (pins 19 and 20) and high voltage pins (ph3/4/5). the design uses special i/o devices without p channel, thus forbidding the push pull configura- tion. in this case there is neither pull up register nor op- tion register. these registers do not exist and so cannot be read or written to. 4.1.3.2 ports c4, c5, d4, d5, f0-f3, g3 these ports offer interrupt capabilities. in this case there is no pull up register since the pull-up is present only when the interrupt feature is selected. this register does not exist and so can- not be read or written to. switching these i/o ports from one state to anoth- er should be done in such a sequence as to pre- vent unwanted side effects. recommended safe transitions are illustrated in figure 14. other tran- sitions are potentially risky and should be avoided, since they are likely to present unwanted side-ef- fects such as spurious interrupt generation. figure 14. recommended i/o state transition diagram ddr mode option 0 input no pull-up, no pull-down, no interrupt 1 output push-pull (or open drain: see note) ddr or mod e option 0 0 input no pull-up, no pull-down, no interrupt 0 1 input interrupt, pull-up 1 0 output open-drain, no pull-up 1 1 output push-pull, no pull-up, no pull-down 11 00 01 interrupt pull-up push-pull no pull-up open-drain no pull-up no pull-down input output output 10 no pull-up no interrupt input no pull-down (reset state) xx = ddr, or
28/117 ST7285C 4.2 serial communications interface 4.2.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the sci of- fers a very wide range of baud rates thanks to the presence of two baud rate generator systems: the first is of conventional type and yields common communications baud rates with standard oscilla- tor frequencies; the second features a program- mable prescaler capable of dividing the input fre- quency by any factor from 1 to 255, thus offering a very wide range of baud rates even with non- standard oscillator frequencies. transmitter and receiver circuits are independent and can operate at different baud rates; indeed, each can select ei- ther type of baud rate generator. external connec- tions are by means of two i/o pins: tdo (port pb0) for the transmit data output and rdi (port pb1) for the receive data input. 4.2.2 features full duplex, asynchronous communications nrz standard format (mark/space) dual baud rate generator systems independently programmable transmission and reception baud rates separate transmit and receive baud rates programmable word length (8 or 9 bits) receive buffer full, transmit buffer empty and end of transmission flags receiver wake-up function by the most signifi- cant bit or by idle line muting function for multiprocessor configurations separate enable bits for transmitter and receiver noise, overrun and frame error detection four interrupt sources with flags overall accuracy better than 1% of baud rate. 4.2.3 serial data format serial data is transmitted and received as frames comprising the following elements: an idle line in the ohigho state prior to transmis- sion or reception. a start bit in the olowo state, denoting the start of each character. character data word (8 or 9 bits), least significant bit first. a stop bit in the ohigho state, indicating that the frame is complete. word length may be selected as being either 8 or 9 bits by programming the m bit in the sccr1 con- trol register. an idle line condition is interpreted on receiving an entire frame of ooneso. a break is interpreted on receiving ozeroso for some multiple of the frame period. 4.2.4 data reception and transmission the following description is best read with refer- ence to the sci block diagram illustrated in figure 1, where it will be noted that the scdr data regis- ter is shown as two separate registers, one for transmitted data and the other for received data. the serial communications data register (scdr) performs a dual function (read and write), since it accesses two separate registers, one for transmis- sion (tdr) and one for reception (rdr). the tdr register provides the data interface between the in- ternal bus and the output shift register for data to be transmitted, while the rdr register provides an in- terface between the input shift register and the in- ternal bus for incoming data. when the scdr is read, the rdr is accessed and its contents are transferred to the data bus. the rdrf (rdr full flag) in the scsr register is set to o1o as soon as the word in the receiver shift reg- ister is transferred to the rdr register. when the scdr is written to, the data word is transferred to the tdr register. the tdre flag (tdr empty) in the scsr register is set to o1o as soon as the word in the tdr is transferred to the transmit shift register. incoming data is received in a serial shift register and then transferred to a parallel receive data register (rdr) as a complete word, thus allowing the next incoming character to be received in the shift register while the current character is still in the rdr. oversampling techniques are used for data recov- ery by discriminating between valid incoming data and noise. 4.2.5 receiver muting and wake-up feature in multiprocessor configurations it is often desira- ble that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overheads for all non addressed receivers. communications protocols in such configurations generally issue the recipient address as a message header.
29/117 ST7285C serial communications interface (cont'd) each receiving device decodes this address head- er under program control and all non addressed receivers may be placed in a sleep mode by means of the muting function, thus avoiding the message contents from generating unnecessary requests for service. this is achieved by inhibiting all reception flags and interrupt generation when muting is enabled. a muted receiver may be re- awakened in one of two ways: by idle line detec- tion or by address mark detection. the wake-up method may be programmed by programming the wake bit in the sccr1 register. receiver wake-up by idle line detection takes place as soon as the receive line is recognised as being idle. an idle line condition is detected upon receiving 10 or 11 consecutive ooneso, depending on whether a word has been defined as compris- ing 8 or 9 data bits. this wake-up method is select- ed by programming the wake bit to o0o. receiver wake-up by address mark detection takes place on receiving a o1o as the most signifi- cant bit of a word, thus indicating that the message is an address. this wake-up method is selected by programming the wake bit to o1o. 4.2.6 baud rate generation the following description is best read with refer- ence to the sci baud rate and external prescaler diagram illustrated in figure 2. the cpu clock is first divided by 16 by the first di- visor block, then again divided by the division fac- tor selected for the first prescaler, indicated by pr. this division factor can be selected to be 1, 3, 4 or 13, depending on the setting of the scp0 and scp1 bits (bits 6 and 7) in the scbrr register (re- fer to the register description). the output from the first prescaler will thus be the cpu clock frequen- cy divided by 16, 48, 64 or 208. this master clock is available both to the conventional baud rate generator and to the external prescaler. the conventional baud rate generator is enabled by setting the relevant section (rx or tx) of the external prescaler to 00h. in this case the master clock frequency is further divided by 1, 2, 4, 8, 16, 32, 64 or 128, depending on the settings of bits sct0, sct1 and sct2 in the case of the transmit- ter, and scr0, scr1 and scr2 in the case of the receiver (refer to the scbrr register description). if the external prescaler receive or transmit baud rate register, psbrt or psbrr is set to a value other than zero, that section of the prescaler will be operational in place of the conventional baud rate generator. the output clock rate sent to the transmitter or to the receiver will be the out- put from the first prescaler divided by a factor ranging from 1 to 255 set in the external prescaler receive or transmit baud rate register. as can be seen the external prescaler option gives a very fine degree of control on the baud rate, whereas the conventional baud rate generator retains in- dustry standard software compatibility. 4.2.7 sci register overview the registers described in the following para- graphs allow full control of the various features and parameters of the serial communications in- terface. refer also to the memory map. 4.2.7.1 data register (scdr) address: 0051h e read/write reset value: xxh contains the received or transmitted data char- acter, depending on whether it is read or written to. 4.2.7.2 control register 1 (sccr1) address: 0053h e read/write reset value: xxh contains bits to select the desired word length and the wake-up mode. bit-7 = r8 receive data bit 8 if bit m is set at one, r8 will be used to store the 9th bit on reception. bit-6 = t8 transmit data bit 8 used to store the 9th data bit of the transmitted word, when 9-bit word length is selected (bit m set to o1o). bit-4 = m word length determines the word length: 0 = 1 start bit, 8 data bits, 1 stop bit 1 = 1 start bit, 9 data bits, 1 stop bit bit-3 = wake wake-up method 1 = address mark 0 = idle line 76543210 r8 t8 - m wake - - -
30/117 ST7285C serial communications interface (cont'd) 4.2.7.3 control register 2 (sccr2) address: 0054h e read/write reset value: 00h contains four control bits which allow interrupts generated by tdr empty, transmit complete, rdr full and idle line to be enabled or disabled. also contains four control bits to enable or disable transmission, reception, receiver wake-up and send break. bit-7 = tie transmitter interrupt enable authorizes an interrupt when set at one and when the tdre (transmission register empty) flag is set to a1o indicating that the last word has been trans- mitted. when tie is at zero this interrupt is disa- bled. bit-6 = tcie transmission complete interrupt en- able this bit set to a1o enables an interrupt when the tc flag (transmission competed) changes to a1o. when tcie is at a0o this interrupt is disabled. bit-5 = rie receiver interrupt enable authorizes an interrupt when set to a1o and when either the rdrf (receive data register full) flag or the or (overspeed on reception) flag is set to a1o, indicating that the last word has been transmit- ted. when tie is set to a0o, this interrupt is disa- bled. bit-4 = ilie idle line interrupt enable this bit at a1o enables an interrupt if the idle flag changes to a1o (which corresponds to an idle line on reception). the interrupt cannot occur if the idle bit is at a0o. bit-3 = te transmitter enable this bit at a1o enables the transmitter. at start-up, the transmitter sends a preamble (ten or eleven ones). during transmission, a a0o pulse on the te bit (a0o followed by a1o) sends a preamble after the current word. setting the te bit to a0o switches the output line to a high impedance state at the end of the word currently being transmitted. bit-2 = re receiver enable the re bit at a1o enables the receiver which be- gins searching for a start bit. the re bit at a0o disables the receiver and resets the associated status bits to a0o (rdrf, idle, or, nf and fe). bit-1 = rwu receiver wake-up the rwu bit at a1o mutes the receiver. the wake- up mode is determined by the wake bit (bit 3 in sccr1). as long as rwu remains at a1o, the flags relating to the receiver cannot rise to a1o. writing a0o to rwu forces an exit from the muted state. as soon as the wake-up sequence is recognized, the rwu bit is forced to a0o. if the wake-up select- ed mode corresponds to the reception of a pream- ble, the rwu bit cannot be set to a1o as long as the reception remains idle. if the selected wake-up mode corresponds to the reception of a a1o on the most significant bit, the reception of this particular word wakes up the receiver and sets the rdrf flag to a1o, which allows the receiver to receive this word normally and to use it as an address word. bit-0 = sbk send break this bit set to a1o tells the transmitter to send a whole number of breaks (all bits at a0o including the stop bit). at the end of the last break the transmitter inserts an extra a1o bit in order to ac- knowledge the start bit. if the sbk bit is set to a1o and then to a0o, the transmitter will send a break word at the end of the current word. 4.2.7.4 status register (scsr) address: 0050h e read only reset value: 1100 0000b contains four flags which denote conditions which can lead to interrupts if the corresponding bits of sccr2 are set: tdr empty, transmit complete, rdr full and idle line. these flags are used for management of the sci interrupt system. also contains three flags which indicate error con- ditions due to overrun, noise and framing. bit-7 = tdre transmit data register empty indicates that the content of the transmission data register has been transferred into the shift register. if the tdre bit is at a0o, it indicates that the trans- mission has not yet occurred and that a write oper- ation into the data register would overwrite previ- ous data. the tdre bit is reset to a0o by an scsr access followed by a write operation into the trans- mission data register. data will not be transferred to the shift register as long as the tdre bit is not reset to a0o. bit-6 = tc transmission complete 76543210 tie tcie rie ilie te re rwu sbk 76543210 tdre tc rdrf idle or nf fe -
31/117 ST7285C serial communications interface (cont'd) the tc bit is automatically set to a1o when trans- mission of a frame containing data, a preamble or a break is complete, if: te = o1o, tdre = o1o, no word is currently being transmitted and no preamble or break is await- ing transmission. te = o0o and the current word or preamble or break has been transmitted the tc bit is a flag indicating that one of the above sequences has occurred. this bit is reset to a0o by an access to the scsr followed by a write opera- tion into the data register or when tdre is reset to a0o. transmitter operation is in no way modified by the status of this bit. bit-5 = rdrf received data ready flag this bit, when set to a1o, indicates that the content of the rdr has been transferred into the scdr. if a frame error or noise has been detected during reception, the corresponding flags will be set. the rdrf bit is reset to a0o by an access to the scsr followed by a data register read operation. bit-4 = idle idle line detect when the idle line detect bit is set it indicates that the receiver idle line is detected (receipt of a mini- mum number of ones (10 when m=0, 11 when m=1) to constitute the number of bits in the frame format. this allows a receiver that is not in the wake-up mode to detect the end of a message or the preamble of a new message or to re-synchro- nize with the transmitter. the idle bit is cleared by accessing the scsr (with idle set) followed by a read of the data register. the idle bit will not be set again until the rdrf bit has been set itself (i.e. a new idle line occurs). the idle bit is not set by an idle line when the receiver wakes up from wake up mode. bit-3 = or overrun error this bit is set to a1o, when the word currently being received in the shift register is ready to be trans- ferred into the data register while the latter is al- ready full (rdrf=o1o). all transfers will remain dis- abled as long as rdrf remains at a1o. data regis- ter content will not be lost but the shift register will be overwritten. the or bit is reset by an access to the scsr followed by a data register read opera- tion. bit-2 = nf noise flag this bit is set to a1o when noise is detected on an acknowledge start bit or a data bit or a stop bit. the nf is set to a1o when the noise is detected at the rising edge of rdrf and is representative of the word present in the data register. this bit does not generate interrupts as it appears at the same time as rdrf which itself generates an interrupt. the nf bit is set to a0o by a scsr read operation followed by a data register read operation. bit-1 = fe framing error this bit is set to a1o when the stop bit is not rec- ognized on reception at the expected moment, fol- lowing either a de-synchronization, excessive noise or when a break is received. the word will, however still be transferred to the data register. as in the case of the nf bit, the few bit does not gen- erate an interrupt as it appears at the same time as rdrf bit. if the word currently being transferred causes both frame error and reception overspeed, it will be transferred and only the or bit will be set to a1o. the fe bit is reset to a0o by a scsr read operation followed by a data register read opera- tion. bit-0 = unused 4.2.7.5 baud rate register (scbrr) address: 0052h e read/write reset value: 00x----xb contains two bits for selection of the first prescaler factor, three bits for selection of the transmitter rate divisor and three bits for the receiver rate divi- sor. bit-7 = scp1 first prescaler msb bit-6 = scp0 first prescaler lsb these 2 prescaling bits allow several standard clock division ranges: bit-5 = sct2 transmitter rate divisor msb bit-4 = sct1 transmitter rate divisor nsb bit-3 = sct0 transmitter rate divisor lsb these 3 bits, in conjunction with the 2 previous bits define the total division applied to the bus clock to yield the transmit rate clock in conventional baud rate generator mode. 76543210 scp1 scp0 sct2 sct1 sct0 scr2 scr1 scr0 scp1 scp0 pr prescaling factor 00 1 01 3 10 4 11 13
32/117 ST7285C serial communications interface (cont'd) this tr factor is used only when the psbrt fine tuning factor is equal to 0; otherwise, tr is re- placed by the psbrt dividing factor. bit-2 = scr2 receiver rate divisor msb bit-1 = scr1 receiver rate divisor nsb bit-0 = scr0 receiver rate divisor lsb these 3 bits, in conjunction with the 2 previous bits define the total division applied to the bus clock to yield the receive rate clock in conventional baud rate generator mode.. this rr factor is used only when the psbrr fine tuning factor is equal to 0; otherwise, rr is re- placed by the psbrr dividing factor. 4.2.7.6 external receive prescaler division register (pscbrr) address: 0055h e read/write reset value: 00h allows setting of the external prescaler rate divi- sion factor for the receive circuit. when the register is set to 00h, the conventional baud rate generator is used for the receive cir- cuit, otherwise the master clock frequency is divid- ed by the binary factor set in the pscbrr register (in the range 1 to 255). 4.2.7.7 external transmit prescaler division register (pscbrt) address: 0057h e read/write reset value: 00h allows setting of the external prescaler rate divi- sion factor for the transmit circuit. when the register is set to 00h, the conventional baud rate generator is used for the transmit cir- cuit, otherwise the master clock frequency is divid- ed by the binary factor set in the pscbrtregister (in the range 1 to 255). sct2 sct1 sct0 tr dividing factor 000 1 001 2 010 4 011 8 100 16 101 32 110 64 1 1 1 128 scr2 scr1 scr0 rr dividing factor 000 1 001 2 010 4 011 8 100 16 101 32 110 64 1 1 1 128 76543210 prbr 7 prbr 6 prbr 5 prbr 4 prbr 3 prbr 2 prbr 1 prbr 0 76543210 ptbr 7 ptbr 6 ptbr 5 ptbr 4 ptbr 3 ptbr 2 ptbr 1 ptbr 0
33/117 ST7285C serial communications interface (cont'd) figure 15. sci block diagram flag control receiv e data register receive data shift register wake up unit receiver control transm it data shift register transmit register data tdo sccr2 rwu sbk re te ilie rie tcie tie tdre tc rdrf idle or nf fe 1 23 467 05 1 2 3 4 5 6 7 scsr transmit control r8 t8 m sccr1 0 1 2 3 4 5 6 7 rdi internal bus sci interrupt wake transmit clock receive clock
34/117 ST7285C serial communications interface (cont'd) figure 16. sci baud rate and external prescaler block diagram receiver rate control transmitter rate control transmitter recei ver pscbrt 7 0 scbrr 7 0 pscbrr 7 0 external prescaler receiver rate control external prescaler transmitter rate control external prescaler cpu clock divide by 16 divide by pr convent ional baud rate generato r clock clock
35/117 ST7285C 4.3 16-bit timer 4.3.1 introduction one or more timers may be present in the mcu, depending on product specification. please refer to the block diagram to ascertain available prod- uct resources, and to the memory map for register addresses. each timer consists of a 16-bit free-running coun- ter driven by a programmable prescaler, as well as the control logic required to implement two input capture and two output compare registers. the timer may be used for a variety of purposes, amongst which pulse length measurement of up to two input signals and generation of up to two out- put waveforms (e.g. pwm). the timer block dia- gram is illustrated in figure 1. pulse lengths and waveform periods can vary from a few microseconds to many seconds, thanks to the programmable prescaler. when running with a 4mhz internal cpu clock, the timer can have a resolution of 0.5, 1 or 2 m s, depending on the set- ting of the clock control bits in the timer control register (tcr2). a software selectable external clock input pin is available. since the timer has a 16-bit architecture, each of its specific functional blocks is associated with a register pair. these registers contain the high or- der byte and the low order byte respectively of the related function. access to the high order byte in- hibits the associated timer function until the low or- der byte is also accessed. correct software procedures should set bit `i' of the condition code register before accessing the high order byte to prevent an interrupt from occur- ring between accesses to the high and low order bytes of any register. in normal operating mode, reading the msb of the input capture register inhibits input capture until the lsb is read. this mechanism allows input cap- ture to be disabled when the pin is connected to an i/o bit. when the pulse width modulation (pwm) and one pulse mode (opm) features are selected to- gether, the pwm mode is the only active one. 4.3.2 counter the key element of the programmable timer is a 16-bit free running counter and its associated reg- ister. the counter is preceeded by a prescaler which divides the internal clock by two, four or eight, depending on the setting of the clock control bits of the timer control register (tcr2), as illus- trated in table 1 below. table 7. clock control bits software can read the counter at any time without affecting its value, either from the counter regis- ters or from the alternate counter registers. the only difference between these two read-only regis- ter pairs is the way the overflow flag (tof) is han- dled during a read sequence. a read sequence where only the least significant byte of the free running counter is read (from either the counter register or the alternate counter register), will receive the lsb of the count value at the time of the read. a read of the most significant byte (from either the counter register or the alternate counter regis- ter) simultaneously returns the msb of the count value and causes the lsb to be transferred to a buffer. the buffered value remains unchanged un- til the 16-bit read sequence is completed, even if the user reads the msb several times. the read sequence is completed by reading the lsb, which actually returns the buffered value. as shown in figure 2, figure 3 and figure 4, the free-running counter is set to fffch on reset. during a power-on reset (por) cycle, the coun- ter is loaded with fffch and begins running. cc1 cc0 clock divisor 00 4 01 2 10 8 1 1 external clock
36/117 ST7285C 16-bit timer (cont'd) figure 17. timer block diagram mcu-peripheral interface counter alternate register output compare registe r output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st7 internal bus latch1 ocp1 icp1 tclk cpu clock timer interrupt icf2 icf1 0 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icp2 latch2 ocp2 8 8 8low 16 8 high 16 16 16 16 cc1 cc0 tcr1 tcr2 tsr 6 16 888 8 88 high low high high high low low low exedg exedg port timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture registe r 1 input capture register 2 cc1 cc0 16 bit free running counter
37/117 ST7285C 16-bit timer (cont'd) when the counter rolls over from ffffh to 0000h, the timer overflow flag (tof) of the timer status register (tsr) is set. a timer interrupt is then gen- erated if the toie enable bit of the timer control register (tcr1) is set, provided the i bit of the ccr is cleared. if one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true. the interrupt request is cleared by reading tsr while tof is set, followed by an access (read or write) to the lsb of the counter register. the tof flag is not affected by accesses to the al- ternate counter register. this feature allows si- multaneous use of the overflow function and reads of the free running counter at random times (for example, to measure elapsed time) without risking to clear the tof flag erroneously. accesses to the timer without the intention of servicing the tof flag should therefore be performed to the alternate counter register while only the tof service rou- tine accesses the counter register. the free running counter can be reset under soft- ware control, by writing to the lsb of the counter register or of the alternate counter register. the counter and the prescaler are then configured to their reset conditions. this reset also completes any 16-bit access sequence. all flags and enable bits are unchanged. the value in the counter registers repeats every 131,072, 262,144, or 524,288 internal processor clock cycles, depending on the clock control option selected in tcr2. as shown in the timing dia- grams, the counter increment is triggered by a fall- ing edge of the cpu clock. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). 4.3.3 external clock when the external clock is selected by setting the relevant clock control bits in tcr2, the counter clocks on each external clock rising edge, if exedg in tcr2 is set, or the falling edges if reset, and is synchronised with the falling edge of the in- ternal cpu clock. at least four falling edges of the cpu clock must occur between two consecutive active edges of the external clock; thus the external clock frequen- cy must be less than a quarter of the cpu clock frequency. the parasitic pulses generated by the extedg and extclke transitions are filtered during two clock periods, so the manipulation of the external clock control bits must occur before or after two in- ternal clock periods.
38/117 ST7285C 16-bit timer (cont'd) figure 18. timer timing diagram, internal clock divided by 2 figure 19. timer timing diagram, internal clock divided by 4 figure 20. timer timing diagram, internal clock divided by 8 cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset internal timer clock t10 counter register overflow flag tof fffc fffd 0000 0001 cpu clock internal reset internal timer clock t10 counter register overflow flag tof internal timer clock t00 cpu clock internal reset internal timer clock t10 counter register overflow flag tof fffc fffd 0000 internal timer clock t00
39/117 ST7285C 16-bit timer (cont'd) 4.3.4 input capture the timer features two input capture registers and an input capture interrupt enable bit. the input capture registers (icr1 and icr2) each consist of two 8-bit registers: the most signif- icant byte registers (ichr1 and ichr2), and the least significant byte registers (iclr1 and iclr2). in the following description, the variable i may rep- resent 1 or 2. icr i is a read-only registers used to latch the val- ue of the free running counter after a defined tran- sition is sensed by the input capture edge detector at pin icap i . this transition is software program- mable through the iedg i bit of the timer control register (tcr i ). when iedg i is set, a rising edge triggers the capture; when iedg i is low, the cap- ture is triggered by a falling edge. when an input capture occurs, the icf i flag in the timer status register (tsr) is set. an interrupt is requested if the interrupt enable bit, icie, of tcr1 is set, provided the i bit of the ccr is reset. other- wise, the interrupt remains pending until both con- ditions become true. it is cleared by reading the tsr followed by a read or write of the lsb of icr i . the result stored in icr i is one more than the val- ue of the free running counter on the rising edge of the internal processor clock preceding the active transition on the icap i pin (see figure 5). this de- lay is required for internal synchronization. there- fore, the timing resolution of the input capture sys- tem is one count of the free running counter, i.e. 2, 4 or 8 internal clock cycles, depending on the clock control bits of tcr2. the free running counter is transferred to icr i on each proper signal transition regardless of wheth- er the input capture flag icf i is set or cleared. the icr i always contains the free running counter value which corresponds to the most recent input capture. after reading the msb of icri, transfer of input capture data is inhibited until the lsb is also read. this implies that the minimum pulse period is de- termined by the time required to respond to the in- terrupt and to execute the service routine. reading iclr i does not inhibit transfer of counter data. the minimum pulse period is determined by the time required to read the least significant byte and to perform necessary actions. there is no conflict between reading icr i and the running counter transfer, since they occur on opposite clock edges as shown in figure 5. icr i is undetermined on power-on, and is not af- fected by an external reset. hardware circuitry must provide protection against generating an un- desired input capture when changing the edge sensitivity option of the icap i pin by programming the iedg i bit. during halt mode, if at least one valid input cap- ture edge occurs on the icap i pin, the input cap- ture detection circuitry is armed. this does not set any timer flags, and does not owake-upo the mcu. if the mcu is awoken by an interrupt, the input capture flag will be active, and data corresponding to the first valid edge during halt mode will be present. if halt mode is exited by a reset, the in- put capture detection circuitry is reset and thus, any active edge that occurred during halt mode will be lost. figure 21. input capture timing diagram ff01 ff02 ff03 ff03 cpu clock 2 cpu clock 4 cpu clock 8 internal clock t10 internal clock t11 counter register icapi pin icapi flag icapi register
40/117 ST7285C 16-bit timer (cont'd) 4.3.5 output compare two output compare registers are present: output compare register 1 and output compare regis- ter 2 (ocr1 and ocr2). these registers can be used for several purposes, such as controlling an output waveform or indicating when a period of time has elapsed. the ocmp i pin is associated with the output compare i function ( i = 1 or 2). the output compare registers are unique in that all bits are readable and writable and are not af- fected by the timer hardware or by reset. if a com- pare function is not used, the two bytes of the cor- responding output compare registers can be used as general purpose storage locations. 4.3.5.1 output compare registers the output compare register i (ocr i ) is a 16-bit register, which is made up of two 8-bit registers: the most significant byte register (ochr i ) and the least significant byte register (oclr i ). in this section, the index, i , may be 1 or 2. the content of ocr i is compared with the content of the free running counter once during every timer clock cycles, i.e. once every 8, 4 or 2 internal proc- essor clock periods or 2 external clock periods ac- cording to the clock control bits of the timer con- trol register (tcr2). if match is found, the output compare flag ocf i of the tsr is set and the out- put level bit (olvl i ) of the tcr1 is clocked to the ocmp i pin (see output compare timing diagrams figure 6, figure 7, figure 8). olvl i is copied to the corresponding output level latch and hence, to the ocmp i pin regardless of whether the output compare flag (ocf i ) is set or not. the value in the ocr i and the olvl i bit should be changed af- ter each successful comparison in order to control an output waveform or establish a new elapsed timeout. an interrupt accompanies a successful output compare if the corresponding interrupt enable bit ocie of the tcr1 is set, provided the i-bit of the ccr is cleared. otherwise, the interrupt remains pending until both conditions are true. it is cleared by a read of tsr followed by an access to the lsb of the ocr i . after a processor write cycle to the ochr i regis- ter, the output compare function is inhibited until the oclr i is also written. thus, the user must write both bytes if the msb is written first. a write made to only the lsb will not inhibit the compare function. the minimum time between two succes- sive edges on the ocmp i pin is a function of the software program and the clock control bits of the tcr2. the ocmp i output latch is forced low during reset and stays low until valid compares change it to a high level. because the ocf i flag and the ocr i are undeterminate at power-on and are not affect- ed by an external reset, care must be exercise when initiating the output compare function with software. the following procedure is recommend- ed to prevent the ocf i flag from being set be- tween the time it is read and the write to ocr i : write to ochr i (further compares are inhibited). read the tsr (first step of the clearance of oc- f i , which may be already set). write to oclr i (enables the output compare function and clears ocf i ).
41/117 ST7285C 16-bit timer (cont'd) figure 22. output compare timing diagram, internal clock divided by 8 figure 23. output compare timing diagram, internal clock divided by 4 figure 24. output compare timing diagram, internal clock divided by 2 internal cpu clock internal timer clock t01 internal timer clock t11 counter fffc fffd fffc compare register compare register latch output register flag ocfi and ocmpi pin internal cpu clock internal timer clock t01 internal timer clock t11 counter compare register compare register latch output register flag ocfi and ocmpi pin fffc fffd fffe cpu writes fffd fffd internal cpu clock internal timer clock t01 internal timer clock t11 counter compare register compare register latch output register flag ocfi and ocmpi pin cpu writes ffff ffff fffd fffd fffe ffff 0000 fffc
42/117 ST7285C 16-bit timer (cont'd) 4.3.5.2 forced compare mode the main purpose of the forced compare mode is to facilitate fixed frequency generation. in this section i may represent 1 or 2. when the forced output level i bit (folv i )of tcr1 is written to 1, olvl i is copied to the ocmp i pin. to provide this capability, internal logic allows a single instruction to change olvl i and causes a forced compare with the new value of olvl i .ocf i is not affected, and thus no interrupt request is generated. 4.3.5.3 one pulse mode the one pulse mode enables the generation of a pulse on the occurence of an external event and is programmed via the opm bit in the tcr2 register. the trigger event is applied to the input capture1 pin (icap1); the active edge of the event is flagged by the iedg1 bit in tcr1. then, on an event on icap1, the counter is initial- ized to fffch and olvl2 is loaded on the output compare 1 pin (ocmp1); when the value of the counter is equal to the value of the contents of ocr1, the olvl1 bit is output on the output com- pare 1 pin (ocmp1). no interrupt is generated. (see figure 9). 4.3.5.4 pulse width modulation mode this mode is similar to the one pulse mode, in which the external event is replaced by the output compare 2 event; this mode is programmed via the pwm bit in the tcr2 register. ocr1 then contains the length of the pulse, while ocr2 contains the value of the period; the output compare 2 event causes the counter to be initial- ized to fffch (see figure 10). no interrupt is generated figure 25. one pulse mode timing, iedg1=1; ocr1=2ed0h figure 26. pulse width modulation mode timing, ocr1=2ed0h, ocr2=34e2 counter .... fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 counter 34e2 fffc fffd fffe 2ed0 2ed1 2ed2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2
43/117 ST7285C 16-bit timer (cont'd) 4.3.6 timer registers as can be seen from the memory map, each timer is associated with three control and status regis- ters which are described in detail below, as well as with six pairs of data registers (16-bit values) relat- ing to the two input captures, the two output com- pares, the counter and the alternate counter. these six pairs of data registers are self-explana- tory and need no further description. timer control register 1 (tcr1) address: see memory map e read/write reset value: 0000 0000b bit 7 = icie input capture interrupt enable if icie is set, a timer interrupt is enabled whenever the icf1 or icf2 status flags of tsr are set. if the icie bit is cleared, the interrupt is inhibited. bit 6 = ocie output compare interrupt enable if ocie is set, a timer interrupt is enabled whenev- er the ocf1 or ocf2 status flags of tsr are set. if the ocie bit is cleared, the interrupt is inhibited. bit 5 = toie timer overflow interrupt enable if toie is set, a timer interrupt is enable whenever the tof status flag of tsr is set. if the toie bit is cleared, the interrupt is inhibited. bit 4 = folv2 forced output compare 2 when written to 1, folv2 forces olvl2 to be copied to the ocmp2 pin. folv2 has no effect otherwise. it can only be reset by a system reset. bit 3 = folv1 forced output compare 1 when written to 1, folv1 forces olvl1 to be copied to the ocmp1 pin. folv1 has no effect otherwise. it can only be reset by a system reset. bit 2 = olvl2 output level 2 the olvl2 bit is copied to the ocmp2 pin when- ever a successful comparison occurs at ocr2. bit 1 = iedg1 input edge 1 the value of iedg1 determines which type of level transition on pin icap1 will trigger a free running counter transfer to the icr1. when iedg1 is set, a rising edge triggers the capture, and when it is re- set, a falling edge does. bit 0 = olvl1 output level 1 the olvl1 bit is copied to the ocmp1 pin when- ever a successful comparison occurs at ocr1. timer control register 2 (tcr2) address: see memory map e read/write reset value: 0000 0000b bit 7 = oc1e output compare 1 enable if oc1e is set, the output compare 1 pin (ocmp1) is dedicated to the output compare 1 ca- pability of the timer. if oc1e is reset, this pin is a general use i/o pin. bit 6 = oc2e output compare 2 enable if oc2e is set, the output compare 2 pin (ocmp2) is dedicated the output compare 2 capability of the timer. if oc2e is reset, this is a general i/o pin. bit 5 = opm one pulse mode if opm is set, the input pin icap1 is usable to trig- ger one pulse on the output pin ocmp1; the active transition on icap1 is given by the state of iedg1. the length of the generated pulse depends on the the contents of ocr1. bit 4 = pwm pulse width modulation if pwm is set, the output pin ocmp1 outputs a programmable cyclic signal; the length of the pulse depends on the value of ocr1; the period de- pends on the value of ocr2. bit 3, 2 = cc1-cc0 clock control 00: the internal clock is divided by 4 01: the internal clock is divided by 2 10: the internal clock is divided by 8 11: the external clock is selected as shown in the block diagram. bit 1 = iedg2 input edge 2 the value of iedg2 determines which level transi- tion on pin icap2 will trigger the free running counter transfer to the icr2. when iedg2 is high, a rising edge triggers the capture since when low, a falling edge does. bit 0 = exedg external clock edge the status of exedg determines which type of level transition on the external clock pin exclk will trigger the free running counter. when exedg is set, the active transition is the rising edge; when exedg is reset, the active transition is the falling edge. 70 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 70 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg
44/117 ST7285C 16-bit timer (cont'd) timer status register (tsr) address: see memory map e read only reset value: 0000 0000b the timer status register (tsr) is an 8-bit regis- ter of which the five most significant bits contain read-only status information and the three least significant bits are not used. bit 7 = icf1 input capture flag 1 icf1 is set when a proper edge has been sensed by the input capture edge detector at pin icap1. the edge is selected by the iedg1-bit in tcr. icf1 is cleared by a processor access to the tsr while icf1 is set followed by an access (read or write) to the low byte of icr1 (iclr1). bit 6 = ocf1 output compare flag 1 ocf1 is set when the content of the free running counter matches the content of ocr1. it is cleared by a processor access of tsr while ocf1 is set followed by an access (read or write) to the low byte of ocr1. bit 5 = tof timer overflow tof is set by a transition of the free running coun- ter from ffffh to 0000h. it is cleared by a proces- sor access to tsr while tof is set followed by an access (read or write) to the low byte of the coun- ter low register. tof is not affected by an access to the alternate counter register. bit 4 = icf2 input capture flag 2 icf2 is set when a proper edge has been sensed by the input capture edge detector at pin icap2. the edge is selected by the iedg2-bit in tcr. icf2 is cleared by a processor access to the tsr while icf2 is set followed by an access (read or write) to the low byte of icr2 (iclr2). bit 3 = ocf2 output compare flag 2 ocf2 is set when the content of the free running counter matches the content of ocr2. it is cleared by a processor access of tsr while ocf2 is set followed by an access (read or write) to the low byte of ocr2. bit 2, 1, 0 = unused. 70 icf1 ocf1 tof icf2 ocf2
45/117 ST7285C 4.4 serial peripheral interface 4.4.1 introduction the serial peripheral interface (spi) allows devic- es to be interconnected using a minimum of wires. the spi is synchronous and thus uses a data and a clock signal; in complex arrays, chip select lines may also be used. an spi system may be config- ured as a master and one or more slaves, or as a system in which devices may be either masters or slaves. depending on mcu specifications, one or more spis may be present. 4.4.2 features full duplex, three-wire synchronous transfers master or slave operation 2 mhz (maximum) master bit frequency 4 mhz (maximum) slave bit frequency four programmable master bit rates programmable clock polarity and phase end of transmission interrupt flag write collision flag protection master mode fault protection capability. 4.4.3 functional description a block diagram of the serial peripheral interface (spi) is shown in figure 27. in a master configura- tion, the master start logic receives an input from the cpu (in the form of a write to the spi rate gen- erator data register) and originates the system clock (sck) based on the internal processor clock. this clock is also used internally to control the state controller as well as the 8-bit shift regis- ter. as a master device, data is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle, and then shifted out serially via the mosi pin to the slave device(s). during a read cy- cle, data is received serially from a slave device via the miso pin and loaded into to the 8-bit shift register. when the 8-bit shift register is loaded, its data is parallel transferred to the read buffer and then made available to the internal data bus during a cpu read cycle. in slave configuration, the slave start logic re- ceives a logic low level (from a master device) on the ss pin, and a system clock input (from the same master device) on the sck pin. thus, the slave is synchronized with the master. data from the master is received serially on the slave mosi pin and is loaded into the 8-bit shift register. once the 8-bit shift register is loaded, its data is parallel transferred to the read buffer and then is made available to the internal data bus during a cpu read cycle. during a write cycle, data is par- allel loaded into the 8-bit shift register from the in- ternal data bus and then shifted out serially to the miso pin for application to the master device. figure 29 illustrates the mosi, miso and sck master-slave interconnections. note that the mas- ter ss pin is tied to a logic high level and the slave ss pin to a logic low level. three registers are associated with each spi inter- face: the serial peripheral control register (spcr), the serial peripheral status register (spsr), and the serial peripheral data i/o regis- ter (spdr). these provide control, status, and data functions. these registers are described in detail in the following pages.
46/117 ST7285C serial peripheral interface (cont'd) figure 27. serial peripheral interface block diagram rate generator ss master start logic slave control bits sck mosi miso read read buffer 8-bit shift write state controller flags internal data bus 3 7 8 2 spcr 0ah spif (end tx) 0ch (load) (full) 8 spsr 0bh 8 vr000099 logic start clock internal processor . .
47/117 ST7285C serial peripheral interface (cont'd) 4.4.4 signal description the four basic signals (mosi, miso, sck andss) are described in the following paragraphs. each signal function is described for both the master and slave mode. the spe (serial peripheral enable) bit of the spi control register enables and disables the spi (ac- tive high); when the spi is enabled the associated alternate functions will be attributed to the relevant i/o pins. the spi baud rate is the cpu clock divided by a factor defined by software (2, 4, 16, 32). 4.4.5 master out slave in (mosi) the mosi pin is configured as a data output in the master (mode) device and as a data input in the slave (mode) device. in this manner data is transferred serially from a master to a slave on this line, most significant bit first, least significant bit last. the timing diagrams shown in the electrical characteristics section, control timing subsection, illustrate spi timing and show the relationship between data and clock (sck). four possible timing relationships may be chosen by using control bits cpol and cpha. the master device always allows data to be applied on the mosi line a half-cycle before the clock edge (sck) to allow the slave device to latch the data. both the slave device(s) and a master device must be programmed to similar modes for proper data transfer. when the master device transmits data to a sec- ond (slave) device via the mosi line, the slave device responds by sending data to the master de- vice via the miso line. this implies full duplex transmission with both data out and data in syn- chronized with the same clock signal (which is pro- vided by the master device). thus, the byte trans- mitted is replaced by the byte received and elimi- nates the need for separate transmit-empty and receiver-full status bits. a single status bit spif) is used to signify that the i/o operation is complete. configuration of the mosi pin is a function of the mstr bit in the serial peripheral control register (spcr). when operating as a master, the user should set the mstr bit, defining the mosi pin as an output 4.4.6 master in slave out (miso) the miso pin is configured as an input in a master (mode) device and as an output in a slave (mode) device. in this manner data is transferred serially from a slave to a master on this line, most signifi- cant bit first, least significant bit last. the miso pin of a slave device is placed in the high-impedance state if it is not selected by the master, i.e. itsss pin is at a logic high level. the timing diagram shows the relationship between data and clock (sck). four possible timing relationships may be chosen by using control bits cpol and cpha. the master device always allows data to be applied on the mosi line a half-cycle before the clock edge (sck) in order for the slave device to latch the da- ta. note. the slave device and a master device must be programmed with similar timing modes for proper data transfer. when the master device transmits data to a slave device via the mosi line, the slave device re- sponds by sending data to master device via the miso line. this implies full duplex transmission with both data out and data in synchronized with the same clock signal (one which is provided by the master device.) thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full bits. a single status bit (spif) in the serial periph- eral status register (spsr) is used to signify that the i/o operation is complete. in the master device, the mstr control bit in the serial peripheral control register (spcr) should be set (by the program) to allow the master device to receive data on its miso pin. in the slave de- vice, its miso pin is enabled by the logic high level present on the ss pin: i.e. if ss = 1 the miso pin is placed in the high-impedance state, whereas ifss = 0 the miso pin is an output for the slave device.
48/117 ST7285C serial peripheral interface (cont'd) 4.4.6.1 slave select (ss) the slave select (ss) pin receives an active-low signal which is generated by the master device, in order to enable slave devices to accept data. to ensure that data will be accepted by a slave device, the ss line must be at a logic lowlevel prior to the occurence of sck (system clock), and must remain low until after the last (eighth) sck cycle. figure 28 illustrates the relationship between sck and the data for two different level combinations of cpha, when ss is pulled low. these are : a) cpha = 1 or 0, the first bit of data is applied to the miso line for transfer, and, b) when cpha = 0 the slave device is prevented from writing to its data register. for further infor- mation on the effect the ss input and the cpha have on the i/o data register, refer to the wcl status flag in the oserial peripheral status regis- ter descriptiono. a logic high level on thess sig- nal forces the miso (master in slave out) line to the high-impedance state. also, sck and the mosi (master out slave in) line are ignored by a slave device when its ss signal is at a logic high level. when a device is a master, it constantly monitors its ss signal input for the presence of a logic low level. the master device will become a slave de- vice any time its ss signal input is detected as be- ing at a logic low level. this ensures that only one master controls thess line. when the ss line is detected as being at a logic low level, the master clears the mstr control bit (serial peripheral control register). also, control bit spe in the serial peripheral control register is cleared, causing the serial peripheral interface (spi) to be disabled (spi alternate function pins become inputs). the modf flag bit in the serial peripheral status register is also set to indicate to the master device that another device is attempt- ing to become a master. two devices attempting to be outputs are normally the result of a software error. however, the user system can be configured in such manner as to contain a default master which would automatically otake-overo and restart the system. 4.4.6.2 serial clock (sck) the serial clock is used to synchronize the move- ment of data both in and out of the device via its mosi and miso pins. the master and slave de- vices are capable of exchanging a data byte of in- formation during a sequence of eight clock pulses. since the sck is generated by the master device, the sck line becomes an input on all slave devic- es and synchronizes slave data transfer. the type of clock and its relationship to data are controlled by the cpol and cpha bits in the serial peripher- al control register. the master device generates the sck through a circuit driven by the internal processor clock. two bits (spr0 and spr1) in the serial peripheral control register of the master device select the clock rate. the master device uses the sck to latch incoming slave device data on the miso line and shifts out data to the slave device on the mosi line. both master and slave devices must be operated in the same timing mode as defined by the cpol and cpha bits in the serial peripher- al control register. in the slave device, spr0 and spr1 have no ef- fect on the operation of the serial peripheral inter- face.
49/117 ST7285C serial peripheral interface (cont'd) figure 28 . data clock timing diagram figure 29. serial peripheral interface master slave ss sck miso/mosi (cpol=0, cpha=0) (cpol=0, cpha=1) (cpol=1, cpha=0) (cpol=1, cpha=1) msb lsb 654 3 21 internal strobe for data capture (all modes) sck sck sck vr000098 ss 8-bit shift register master slave spi miso mosi sck ss +5v 0v 8-bit shift register clock generator miso mosi sck ss vr000100
50/117 ST7285C serial peripheral interface (cont'd) 4.4.7 serial peripheral control register (spcr) address: see memory map e read/write reset value: 0xh the serial peripheral control register bits are de- fined as follows. bit-7 = spie serial peripheral interrupt enable when the serial peripheral interrupts enable bit is set a processor interrupt can occur. this forces the proper vector to be loaded into the program coun- ter if the serial peripheral status register flag bit (spif) and /or modf are set. spie does not inhib- it the setting of a status bit. the spie bit is cleared on reset. bit-6 = spe serial peripheral output enalble when the serial peripheral output enable control bit is set, all output drive is applied to the external pins and the system is enabled. when the spe bit is set, it enables the spi system by connecting it to the external pins thus allowing it to interface with the external spi bus. the pins that are defined as outputs depend on which mode (master or slave) the device is in. because the spe bit is cleared on reset, the spi system is not connected to the ex- ternal pins on reset. bit-4 = mstr master the master bit determines whether the device is a master or a slave. if the mstr bit is reset it indi- cates a slave device, whent it is set it indicates a master device. if the master mode is selected, the function of the sck pin changes from an input to an output and the function of the miso and mosi pins are reversed. this allows the user to wire de- vice pins miso to mosi, and mosi to mosi, and sck to sck without incident. the mstr bit is cleared on reset: thus the device is always set in slave mode during reset. bit-3 = cpol clock polarity the clock polarity bit controls the normal or steady state value of the clock when no data is be- ing transferred. the cpol bit affects both the master and slave modes. it must be used in con- junction with the clock phase control bit (cpha) to produce the wanted clock-data relationship be- tween a master and a slave device. when the cp0l bit is reset, it produces a steady-state logic low value on the sck pin of the master device. if the cpol bit is set, a logic high level is present on the sck pin of the master device when data is not being transferred. the cpol bit is not affected by reset. bit-2 = cpha clock phase the clock phase bit controls the relationship be- tween the data on the miso and mosi pins and the clock produced or received at the sck pin. this control has effect in both the master or slave modes. it must be used in conjunction with the clock polarity control bit (cpol) to produce the wanted clock-data relationship. in general the cpha bit selects the clock edge which captures data and allows it to change states. it has its great- est impact on the first bit transmitted (msb) in that it does or does not allow a clock transition before the first data capture edge. the cpha bit is not af- fected by reset. bit-1 = spr1 serial peripheral rate bit 1 bit-0 = spr0 serial peripheral rate bit 0 these two serial peripheral rate bits select one of four baud rates to be used for sck when the de- vice is a master. however, these two bits have no effect in slave mode. the slave device is capable of shifting data in and out at a maximum rate which is equal to the cpu clock. a rate table is given be- low for sck in master mode. the spr1 and spr0 bits are not affected by reset. 70 spie spe - mstr cpol cpha spr1 spr0 spr1 spr0 internal processor clock division factor 00 2 01 4 10 16 11 32
51/117 ST7285C serial peripheral interface (cont'd) 4.4.8 serial peripheral status register (spsr) address: see memory map e read only reset value: 00h the status flags which generate a serial peripher- al interface (spi) interrupt may be blocked by the spie control bit in the serial peripheral control register. the wcol bit does not cause an inter- rupt. the serial peripheral status register bits are defined as follows: bit-7 = spif serial peripheral data transfer flag the serial peripheral data transfer flag bit noti- fies the user that a data transfer between the de- vice and an external device has been completed. with the completion of the data transfer, spif is set, and if spie is set, a serial peripheral interrupt is generated. during the clock cycle spif is being set, a copy of the received data byte in the shift register is moved to a buffer. when the data regis- ter is read, it is the buffer that is read. in the event of an overrun condition, when the master device has sent several bytes of data and the slave de- vice has not responded to the first spif, only the first byte sent is contained in the receive buffer, and all other bytes are lost. data transfer is initiated by the master device writ- ing to its serial peripheral data i/o register. clearing the spif bit is accomplished by a soft- ware sequence which accesses the serial periph- eral status register while spif is set, followed by a write or read operation on the serial peripheral data i/o register. in the master device, while spif is set, all writes to the serial peripheral data i/o register are inhibit- ed until the serial peripheral status register is read. in the slave device, spif can be cleared (using a similar sequence) during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition. the spif bit is cleared on reset. bit-6 = wcol write collision status bit the write collision status bit informs the user that an attempt was made to write to the serial periph- eral data i/o register while a data transfer was taking place with an external device. the transfer continues uninterrupted, and therefore a write will be unsuccessful. a oread collisiono cannot occur, since the received data byte is placed in a buffer in which access is always synchronous with the mcu operation. if a owrite collisiono occurs, wcol is set but no spi interrupt is generated. the wcol bit is a status flag only. clearing the wcol bit is accomplished by a soft- ware sequence of accessing the serial peripheral status register while wcol is set, followed by: 1) a read of the serial peripheral data i/o register prior to the spif bit being set, or 2) a read or write of the serial peripheral data i/o register after the spif bit is set. a write to the serial peripheral data i/o register (spdr) prior to the spif bit being set, will result in generation of another wcol status flag. both the spif and wcol bits will be cleared in the same sequence. if a second transfer has started while trying to clear the (previously set) spif and wcol bits with a clearing sequence comprising a write to the serial peripheral data i/o register, only the spif bit will be cleared. a collision of a write to the serial peripheral data i/o register while an external data transfer is tak- ing place can occur both in the master mode and the slave mode, although with proper program- ming the master device should have sufficient in- formation to preclude this collision. collision in the master device is defined as a write of the serial peripheral data i/o register while the internal rate clock (sck) is in the process of trans- fer. the signal on the ss pin is always at a logic high level on the master device. collision in a slave device is defined in two sepa- rate modes. a problem arises in a slave device when the cpha control bit is reset. when cpha is reset, data is latched on the occurence of the first clock transition. the slave device does not have any way of knowing when that transition will occur; therefore, the slave device collision occurs when it attempts to write the serial peripheral data i/o register after its ss pin has been pulled low. if the cpha bit is reset, the ss pin on the slave device freezes the data in its serial peripheral data i/o register and does not allow it to be altered. the master device must raise the ss pin of the slave device to a logic high level between each byte it transfers to the slave device 70 spif wcol - modf - - - -
52/117 ST7285C serial peripheral interface (cont'd) the second collision mode is defined by the cpha control bit being set. with the cpha bit set, the slave device will be receiving a clock (sck) edge prior to the latch of the first data transfer. this first clock edge will freeze the data in the slave device i/o register and allow the msb on to the external miso pin of the slave device. a logic low state on the ss pin enables the slave device, however, data is not output on the miso pin until the first edge of the data transfer clock. the wcol bit will only be set if the i/o register is accessed while a transfer is taking place. in this second collision mode, a master device can hold a slave device's ss pin low during the transfer of several bytes of data without this causing any problems. unlike other spi interfaces, there is no special case of collision which remains undetected by the wcol bits. the wcol bit is totally reli- able with regard to collision detection. since the slave device is operating asynchronous- ly with the master device, the wcol bit may be used as an indicator of a collision occurence. this helps alleviate the user from a strict real-time pro- gramming effort. the wcol is cleared on reset. bit-4 = modf mode fault flag the function of the mode fault flag is defined for the master mode (device). if the device is a slave device the modf bit will be prevented from tog- gling from reset to set; however, this does not pre- vent the device from being in the slave mode with the modf bit set. the modf bit is normally reset, and is set only when the master device has itsss pin pulled low. toggling the modf bit to the set state affects the internal serial peripheral interface (spi) system in the following ways: a) modf is set and spi interrupt is generated if spie is set. b) the spe bit is forced to a reset state. this blocks all output from the device and disables the spi system. c) the mstr bit is forced to a reset state, thus forcing the device into the slave mode. clearing the modf is accomplished by a software sequence which accesses the serial peripheral status register while modf is set, followed by a write to the serial peripheral control register. to avoid multiple slave conflicts in a system com- prising several mcus, the ss pin must be pulled high during the clearing sequence of modf. con- trol bits spe and mstr may be restored to their original set state during this clearing sequence, or after the modf bit has been cleared. hardware does not allow the user to set the spe and mstr bits while modf is set, unless this occurs during the proper clearing sequence. the modf flag bit indicates the possible occurrence of a multimaster conflict for system control, and allows proper exit from normal system operation to reset or to a de- fault system state. the modf bit is cleared on re- set.
53/117 ST7285C serial peripheral interface (cont'd) 4.4.9 serial peripheral data i/o register (spdr) address: see memory map e read/write reset value: xxh the serial peripheral data i/o register is used to transmit and receive data on the serial bus. only a write to this register will initiate transmission/re- ception of another byte and this will only occur in the master device. a slave device writing to its data i/o register will not initiate a transmission. af- ter having transmitted a byte of data, the spif sta- tus bit is set in both the master and slave devices. a write or read of the serial peripheral data i/o register, after accessing the serial peripheral status register with spif set, will clear spif. during the clock cycle the spif bit is being set, a copy of the received data byte in the shift register is being moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. during an overrun condi- tion, when the master device has sent several bytes of data and the slave device has not inter- nally responded to clear the first spif, only the first byte is contained in the receive buffer of the slave device; all others are lost. the user may read the buffer at any time. the first spif must be cleared by the time a second transfer of data from the shift register to the read buffer is initiated, oth- erwise an overrun condition will exist. a write to the serial peripheral data i/o register is not buffered, and data is placed directly in the shift register for transmission. the ability to access the serial peripheral data i/o register is limited when a transmission is taking place. please refer to the description of the wcol and spif status bits in order to fully appreciate the rules governing the use of the serial peripheral data i/o register. 4.4.10 single master and multimaster configurations there are two types of spi systems, single master and multimaster. a typical single master system may be configured, using one mcu as the master and four others as slaves. the mosi, miso and sck pins are all wired to equivalent pins on each device. the mas- ter device generates the sck clock, whereas the slave devices all receive it. since the mcu master device is the bus master, it internally controls the function of its mosi and miso lines, thus writing data to the slave devices on the mosi and read- ing data from the slave devices on the miso lines. the master device selects the individual slave de- vices by using four pins of a parallel port to control the four ss pins of the slave devices. a slave de- vice is selected when the master device pulls its ss pin low. the ss pins are pulled high, thus dis- abling the slave devices during reset, since the master device ports will be forced as inputs. note that slave devices need not be enabled in a mutually exclusive fashion, except in order to pre- vent bus contention on the miso lines. an exam- ple of this is a write to several display drivers to clear a display using a single i/o operation. to ensure that proper data transmission takes place between the master device and a slave de- vice, the master device may ask the slave device to respond by echoing a previously received data byte (this data byte can be inverted, or at least be different from the last one sent by the master de- vice). the master device will always receive the previous byte back from the slave if all miso and mosi lines are connected and the slave has not written its data i/o register. other transmission se- curity methods may be defined using ports as handshake lines, or by means of data bytes con- taining command fields. a multimaster system may also be configured by the user. an exchange of master control can be implemented by adopting a handshake scheme using the i/o ports, or by an exchange of code messages via the serial peripheral interface sys- tem. the principal device controls are the mstr bit in the serial peripheral control register and the modf bit in the serial peripheral status reg- ister. 70 xxxxxxxx
54/117 ST7285C 4.5 i 2 c bus interface 4.5.1 introduction the i 2 c bus interface serves as an interface be- tween the mcu and the serial i 2 c bus. it provides both multimaster and multislave functions, and controls all i 2 c bus-specific sequencing, protocol, arbitration and timing. 4.5.2 general features parallel bus /i 2 c protocol converter multi-master capability interrupt generation standard i 2 c mode/fast i 2 cmode 7-bit addressing/10-bit addressing 4.5.2.1 i 2 c master mode features: flag indicating when the i 2 c bus is in use flag indicating the loss of arbitration flag indicating the end of the byte transmission transmitter/receiver flag clock generation 4.5.2.2 i 2 c slave mode features: start bit detection flag detection of a misplaced start or stop condition detection of a problem during transfer address matched detection general call detection flag indicating the end of the byte transmission transmitter/receiver flag 4.5.3 functional description in addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. the interrupts are enabled or disabled by software. the interface is connected to the i 2 c bus by a data pin (sda) and by a clock pin (scl). it can be connected both with a standard i 2 c bus and a fast i 2 c bus. this selection is made by soft- ware. the interface can operate in the four following modes: master transmitter master receiver slave transmitter slave receiver when it is inactive, it operates in slave mode. this interface enables the multimaster function thanks to an automatic switch between master and slave mode in the event of a loss of arbitration: the slave process is always active when a start condi- tion is detected on the sda line. when acting as master, it initiates a data transfer and generates the clock signal. a serial data transfer always be- gins with a start condition and ends with a stop condition. both start and stop conditions are soft- ware generated in master mode. in slave mode, the interface is capable of recognising its own ad- dress (7-bit or 10-bit), a general call address or a start byte. the general call may be enabled or dis- abled by software. data and addresses are transferred as 8-bit bytes, msb first. the first byte following the start condi- tion in 7-bit addressing (two first bytes in 10-bit ad- dressing) is the address byte; it is always transmit- ted in master mode. a 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the re- ceiver must send an acknowledge bit to the trans- mitter. acknowledge may be enabled and disabled by software. when in transmitter mode, the interface waits for the mcu to write the byte in the data register, by holding the clock line low before transmission; when in receiver mode, it waits for the mcu to read the byte in the data register by holding the clock line low after reception. the i 2 c bus interface has seven internal registers. three of these are used for interface initialization (own address registers and clock control regis- ter). the remaining four registers are used during data transmission/reception (data register, con- trol register and status register). the scl frequency (f scl ) is controlled by a pro- grammable clock divider which depends on the i 2 c bus mode. the i 2 c interface address is stored in two registers (oar) in order to allow 10-bit ad- dressing. the peripheral enable bit (bit 6) of the i 2 c control register activates the i 2 c interface and configures the i/o as i 2 c pins. the speed of the i 2 c interface may be selected between 100khz and 400khz. when the i 2 c cell is enabled, pa4 and pa6 are configured as open-drain. in this case, the external pull-up resistance should be 10k w or more. when the i 2 c cell is disabled, pa4 and pa6 revert to being standard i/ o port pins.
55/117 ST7285C i 2 c bus interface (cont'd) figure 30. i 2 c interface block diagram data register data shift register comparator own address registe r clock control register status registe r 1 control register control data clock control sda scl logic ddc2b address status registe r 2 vsync it buff dmaack dma data bus control signals interr upt
56/117 ST7285C i 2 c bus interface (cont'd) 4.5.4 eprom/rom i c compatibility application note in order to insure full compatibility between the eprom and the rom versions of the st7285 mi- crocontroller, certain timing conditions have to be respected when using the i 2 c interface. otherwise the i 2 c interface of the st72e85 can: detect an unexpected start or stop condi- tion with bus error detection generate unexpected btf flag settings unexpected start or stop condition detec- tion in the st72e85 device, due to the synchronisation between the i 2 c peripheral and the f cpu (4.332mhz), an unexpected start or stop con- dition can be detected in slave mode. this gener- ates an unexpected bus error and sets the berr bit in the sr2 register. to avoid this effect, the following i c timing has to be respected: tsu dat >1/f cpu ~ 230,84ns thd dat >1/f cpu ~ 230,84ns in the rom version of the st7285, the i 2 c periph- eral and f cpu are asynchronous, so no unexpect- ed start or stop condition can be detected. unexpected btf flag setting after a stop con- dition due to the reason described in the previous para- graph, the btf flag can be set unexpectedly in the i 2 c interface of the st72e85 after a stop condi- tion is detected in slave mode. to recover from this condition, reset and subse- quently set the pe bit in the cr register when the stopf and btf flags are set at the same time af- ter a stop condition detection. the i 2 c interface is not subject to this effect in the rom version of the st7285. figure 31. i c timing diagram sda scl tsu dat thd dat data bit start bit
57/117 ST7285C i 2 c bus interface (cont'd) 4.5.5 register description clock control register (ccr) address: 002bh e read / write reset value: 00h b7: fm/sm fast / standard i 2 cmode when the bit is set to 1 the interface operates in the fast i 2 c bus mode. when the bit is set to 0 the interface operates in the standard i 2 c bus mode. b6-0: d6-d0 7 bit divider programming implementation of a programmable clock divider in standard i 2 c mode: fscl = phi1/(2x([d6..d0]+2)); in this case, fscl varies between 15.75khz and 100 khz (if phi1=4mhz). in fast i 2 c mode: fscl = phi1/(3x([d6..d0]+2)); in this case, fscl varies between 10.5 khz and 333khz (if phi1=4mhz). table 8. example of scl frequency with phi1 = 4 mhz in standard i 2 c mode 70 fm/sm cc6 cc5 cc4 cc3 cc2 cc1 cc0 fm/sm d6 d5 d4 d3 d2 d1 d0 fscl(khz) 0 0010010 100 0 0011011 70 0 0100110 50 0 1001110 25 0 1111111 1 5.75 1 0000010 333 1 0000101 190 1 0000110 167 1 0001101 89 1 0011011 43 1 1111111 10.5
58/117 ST7285C i 2 c bus interface (cont'd) data register (dr) address: 002eh e read / write reset value: 00h in transmitter mode, dr contains the next byte of data which is to be applied to the shift register. the byte transmission begins after the dr write by the microcontroller. in receiver mode, dr contains the last byte of data received from the shift register. the next byte re- ceipt begins after the dr read by the microcontrol- ler. own address register 1 (oar1) address: 002ch e read / write reset value: 00h in 7-bit addressing, [add7..add1] are the ad- dress of the peripheral. in 10-bit addressing, [add7..add0] are the least significant bits of the address of the peripheral. own address register 2 (oar2) address: 002dh e read / write reset value: 00h b7-3 = reserved. b2-1 = [adde2..adde1] are the most significant bits of the address of the peripheral in 10-bit ad- dressing. in 7-bit addressing, the first byte following the start condition is the address byte. the least significant bit is the data direction bit. in 10-bit addressing, the first two bytes following a start condition are the address bytes. the first sev- en bits of the first byte are the combination 11110xx of which the last two bits are the two most significant bits of the 10-bits addressing; the eighth bit is the data direction bit. the second byte con- tains the remaining 8 bits of the 10-bit address. b0 = reserved. various combinations of read/write formats in 10- bit addressing: master-transmitter/slave-receiver when a 10-bit address follows a start condition (s), each slave compares the first seven bits of the first byte of the slave address (11110xx) with its own address and tests the eighth bit. if the slave finds a match, it generates an acknowledge (a1) and it compares the eight bits of the second byte (xxxxxxxx) with its own address. if the slave finds a match, it generates an acknowledge (a2). the slave will remain addressed until it receives a stop condition or a repeated start condition fol- lowed by a different slave address. master-receiver/slave-transmitter the direction of the transfer is changed after the second data direction bit. up to the acknowledge bit a2, the procedure is the same as the one de- scribed for a master-transmitter/slave-receiver. after a repeated start condition, the slave remem- bers that it was addressed before. then it com- pares the seven bits of the first byte (11110xx) with its own address. 70 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 70 add7 add6 add5 add4 add3 add2 add1 add0 70 -----adde2adde1- s slave_address 1st 7bits 0a1 slave_adress 2nd byte a2 data a s slave_adress 1st 7bits 0a1 slave_adress 2nd byte a2 data sr slave_adress 1st 7bits 1 a data a
59/117 ST7285C i 2 c bus interface (cont'd) control register (cr) address: 0028h e read / write reset value: 00h b7-6 = reserved. b5: pe peripheral enable 1 : master/slave capability. 0 : peripheral disabled ( all outputs are released). when this bit is reset, all the bits of the control reg- ister and the status register except the stop bit are reset. pe selects the alternate function on the corre- sponding i/o. this bit is set by software and it is cleared by soft- ware or by a reset. b4: engc enable general call when this bit is set, the peripheral acknowledges the general call address. engc bit is set or cleared by software. it is cleared when the peripheral is disabled (pe=0) or by reset. b3: start generation of a start condition when the start bit is set in slave mode, the inter- face generates a start condition as soon as the bus is free. in master mode, it generates a repeat- ed start condition. then an interrupt is generated if ite is set. this bit is set by software and is cleared by soft- ware, when the peripheral is disabled (pe=0) or by reset. it is automatically cleared after the start con- dition is sent. b2: ack acknowledge level when this bit is set, an acknowledge is returned after an address byte is received or after a data byte is received. when it is cleared, no acknowledge is returned. it is set by software and it is cleared by software, when the peripheral is disabled (pe=0) or by reset. b1: stop generation of a stop condition if the stop bit is set in master mode then a stop condition is generated after the transfer of the cur- rent byte or after that the current start condition is sent. if it is set in slave mode then both scl and sda lines are released in order to recover from an error condition and the peripheral waits for a detection of a start or a stop condition. then the interface waits for a stop or a start condition on the lines. this bit can be cleared by software. it is automati- cally cleared after the stop condition is sent on the scl line in master mode or by reset. b0: ite interrupt enable when the interrupt enable bit is set, the i 2 c inter- face interrupt is generated after anyone of these following conditions a start condition is generated in master mode. the address is matched in slave mode while the ack flag is at a logic high. a data byte has been received or is to be trans- mitted. a loss of arbitration of the bus to another master in master mode. a misplaced start or stop condition is detected there is no acknowledge. a stop condition has been detected in slave mode. while the ite flag is set, an interrupt is generated, scl is hold low and the transfer is suspended except when a loss of arbitration or a detection of a stop condition have been detect- ed. ite is reset by software, when the peripheral is disabled (pe=0) or by reset. 70 - - pe engc start ack stop ite pe = 0 pe = 1 pa6 = normal i/o pa6 = i 2 c data pa4 = normal i/o pa4 = i 2 c clock
60/117 ST7285C i 2 c bus interface (cont'd) status register 1 (sr1) address: 0029h e read only reset value: 00h b7: sr2f status register 2 flag sr2f is set when at least one flag in the status register 2 is set. it is cleared when all these flags are reset. b6: add10 10 bit master addressing mode add10 is set when the 10 bit addressing mode header (o11110xxxo) is sent as the first address byte. when this bit is set, an interrupt is sent to the microcontroller if ite is set this bit is cleared by a read of the status register, followed by a write in the data register. it is also cleared when the peripheral is disabled (pe=0) or by reset. b5: tra transmitter/receiver tra is set when the interface is in data transmis- sion mode. it is cleared by the detection of a stop condition, by a loss of the bus arbitration (arlo set). it is also cleared when the peripheral is disabled (pe=0) or by reset. b4: busy bus busy busy bit is active when there is a communication in progress on line. the detection of the communications is always ac- tive (even if the peripheral s disabled). this bit is set by the detection of a start condition and it is cleared by the detection of a stop condi- tion or by reset. b3: btf byte transfer finished - in transmitter mode, btf bit is set after the trans- mission of a data byte and an acknowledge clock pulse. it is cleared by a read of the status register (with btf set), followed by a write in the data register. in receiver mode, btf bit is set after the reception of the acknowledge of a byte. it is cleared by a reading of the status register (with btf set), followed by a read of the data reg- ister. it is also cleared when the peripheral is disabled (pe=0) or by reset. when btf is set, the i 2 c interrupt occurs if ite is set. then the microcontroller must access the data register. b2: adsl addressed as slave adsl bit is set when the address comparator rec- ognizes either its own slave address or the gener- al call address. when this bit is set , an interrupt is sent to the microcontroller if ite is set. this bit is cleared by a read of the status register (when adsl is set). it is also cleared when the pe- ripheral is disabled (pe=0) or by reset. b1: m/sl master/slave m/sl bit is set when the interface generates a start condition. when it is set, the interface oper- ates in master mode. it is cleared by the detection of a stop condition, by a loss of arbitration, by reset or when the pe- ripheral is disabled (pe=0). b0: sb start bit ( in master mode) in master mode , sb bit is set when the hardware has generated a start condition. when this bit is set, an interrupt is sent to the microcontroller if ite is set. then the microcontroller must write the ad- dress byte in the data register. this bit is cleared by a read of the status register (when sb is set), followed by a write in the data register. it is also cleared when the peripheral is disabled (pe=0) or by reset. 70 sr2f add10 tra busy btf adsl m/sl sb
61/117 ST7285C i 2 c bus interface (cont'd) status register 2 (sr2) address: 002ah e read only reset value: 00h b7-5 = reserved. b4: af acknowledge failure the acknowledge failure bit is set when no ac- knowledge is returned. if this bit is set, then an in- terrupt is sent to the microcontroller if ite is set. during this interrupt, the scl line is not hold low. this bit is cleared by a read of the status register. it is also cleared when the peripheral is disabled (pe=0) or by reset. b3: stopf stop detection flag (in slave mode) stopf bit is set when a stop condition is detected on the scl line after an acknowledge of byte. when this bit is set, an interrupt is sent to the mi- crocontroller if ite is set. during this interrupt, the scl line is not hold low. this bit is cleared by a read of the status register (when stopf is set). it is also cleared when the pe- ripheral is disabled (pe=0) or by reset. b2: arlo arbitration lost arlo is set when the i 2 c interface loses the arbi- tration of the bus to another master. after arlo is set, the interface operates in slave mode (m/sl at a logic low) and an interrupt is generated if ite is set. during this interrupt, the scl line is not hold low. this bit is cleared by a read of the status register. it is also cleared when the peripheral is disabled (pe=0) or by reset. b1: berr bus error berr bit is set when a misplaced start or stop condition is detected. if this bit is set, then an inter- rupt is sent to the microcontroller if ite is set. dur- ing this interrupt, the scl line is not hold low. the bus error flag bit is cleared by a read of the status register (when berr is set). it is also cleared when the peripheral is disabled (pe=0) or by reset. b0: gcal general call (slave mode) if engc is set, gcal is set following detection of a general call address. it is cleared by the detection of a stop condition, by reset or when the peripheral is disabled (pe=0). 4.5.6 i 2 c state machine: in i 2 c mode, the i 2 c interface always operates in slave mode (m/sl at logic low level) except when it initiates a transmission or a receive sequence. it enables the multimaster function with an auto- matic switch from master mode to slave mode when the interface loses the arbitration of the i 2 c bus. so, the slave process is active both in slave mode and in master mode. 4.5.6.1 slave mode as soon as a start condition is detected, the ad- dress word is received from the sda line and it is sent to the shift register; then it is compared with the interface address. address no matched: the state machine is reset and it waits for another start bit. address matched: the addressed as slave bit (adsl) is set and an acknowledge bit is sent to the master if ack is set. so an interrupt is sent to the microcontroller if ite is set; it then waits for the microcontroller to read status register 1 by holding the scl line low. then, depending on the data direction bit (least significant bit), and after generating an acknowl- edge, the slave must enter send or receive mode. 4.5.6.2 slave receiving the slave receives words from the sda line into the shift register and it sends them to the data reg- ister. after each word it generates an acknowledge bit if the enable acknowledge flag is set. when the acknowledge bit is sent, the btf flag is set and an interrupt is generated if ite is set.then it waits for the microcontroller to read the data register by holding the scl line low. - detection of a stop or a start condition during a byte reception: the berr flag is set and an inter- rupt is generated. - detection of a start condition after an acknowl- edge time-slot: the state machine is reset and starts a new process. - detection of a stop condition after an acknowl- edge time-slot: the slave state machine is reset. then the sstop flag is set and an interrupt is generated if ite is set. - the stop bit is set in the control register: the state machine is reset after transfer of the current byte. 70 - - - af stopf arlo berr gcal
62/117 ST7285C i 2 c bus interface (cont'd) 4.5.6.3 slave sending the slave waits for the microcontroller to write in the data register. then it receives data in the shift register and sends it on the sda line. when the acknowledge bit is received, the btf flag is set and an interrupt is generated if ite is set. - detection of a stop or start condition during a byte transfer: the state machine is reset, the berr flag is set and an interrupt is generated. - detection of a start condition after an acknowl- edge time-slot: the state machine is reset and it starts a new process. so, the flag adsl is set and an interrupt is generated if ite is set. - detection of a stop condition after an acknowl- edge time-slot: the state machine is reset. then the flag sstop is set and an interrupt is generat- ed if ite is set. 4.5.6.4 master mode the interface operates in master mode after gen- erating a start condition. so, the start flag must be set in the control register and the i 2 c bus must be free (busy bit at logic low level). once the start condition is generated, the m/sl and sb flags are set and an interrupt is generated if ite is set. the interface waits for the microcon- troller to write the slave address in the data reg- ister by holding the scl line low. the address byte is then sent on the sda line, an acknowledge clock pulse is sent on the scl line and an interrupt is generated if ite is set. the in- terface waits for the mcu to write to the control register by holding the scl line low. if there is no acknowledge, the af flag is set and the master must write a start or a stop in the control register. the state machine then enters a send or a receive process, depending on the state of the data direc- tion bit (least significant bit); an interrupt is gener- ated if ite is set. if the master loses control of bus arbitration, there will be no acknowledge. the af flag is set and the master must write a start or a stop in the control register; the arlo flag is set, the m/sl flag is cleared and the process is reset. an interrupt is generated if ite is set. 4.5.6.5 master sending the master waits for the mcu to write in the data register by holding the scl line low. then the byte is received in the shift register and is sent on the sda line. the btf flag is set and an interrupt is generated if ite is set. - detection of a stop or of a start condition during a byte transfer: the berr flag is set and an inter- rupt is generated if ite is set. - the stop bit is set in the control register: a stop condition is generated after the transfer of the cur- rent byte, the m/sl flag is cleared and the state machine is reset. then an interrupt is generated if ite is set. - the start bit is set in the control register: the state machine is reset and it starts a new process. the sb flag is set and an interrupt is generated if ite is set. - there is no acknowledge: the af flag is set and an interrupt is generated if ite is set. 4.5.6.6 master receiving the master receives a byte from the sda line into the shift register and it sends it to the data regis- ter. so, it generates an acknowledge bit if the ack bit is set and it generates an interrupt if ite is set. then it waits for the microcontroller to read the data register by holding scl line low. - a detection of a stop or a start condition during a byte reception: the flag berr is set and an inter- rupt is generated if ite is set. - the stop bit is set in the control register: a stop condition is generated after the transfer of the cur- rent byte, the m/sl flag is cleared and the state machine is reset. then an interrupt is generated if ite is set. - the start bit is set in the control register: the state machine is reset and starts a new process. so, the flag sb is set and an interrupt is generated if ite is set.
63/117 ST7285C i 2 c bus interface (cont'd) transfer sequencing: master transmitter: (m/sl=1) it1: sb =1. this interrupt is cleared by a read of sr1 followed by a write in dr. it2: this interrupt is cleared by a read of sr1 followed by a write in cr and in dr. it3: btf=1; tra=1. this interrupt is cleared by a read of sr1 followed by a write in dr. master receiver: (m/sl=1)it4: this interrupt is cleared by a read of sr1 followed by a write in cr. it5: btf=1. this interrupt is cleared by a read of sr1 followed by a read of dr. slave transmitter: (m/sl=0) it6: adsl =1. this interrupt is cleared by a read of sr1 followed by a write in dr. it7: btf=1, tra=1. this interrupt is cleared by a read of sr1 followed by a write in dr. it8: stopf=1. this interrupt is cleared by a read of sr2. slave receiver: (m/sl=0) it9: adsl =1. this interrupt is cleared by a read of sr1. it10: btf=1. this interrupt is cleared by a read of sr1 followed by a read of dr. 10 bits addressing (master): master: it11: add10=1. this interrupt is cleared by a read of sr1 followed by a write in dr. slave: during it1,2,3,4,5,6,7,9,10,11 the scl line is hold low. s: start; p: stop; a: acknowledge; it: interrupt. detailed timing information is available in the electrical characteristics. s it1 add a it2 it3 data a it3 data a it3 p s it1 add a it4 data a it5 data a it5 p s add a it6 it7 data a it7 data a it7 p it8 s add a it9 data a it10 data a it10 p it8 s add a it11 add a it2 s add a add a
64/117 ST7285C 4.6 a/d converter (adc) 4.6.1 introduction the on-chip analog to digital converter peripheral is a single 8-bit successive approximation ratio- metric monotonic adc, to which up to 8 different analog voltages (depending on device specifica- tion as illustrated in block diagram) may be ap- plied from external sources. the result of the con- version is stored in the 8-bit data register. the a/ d converter is controlled through the adc control/ status register. 4.6.2 functional description the a/d converter is enabled by setting the a/d converter on bit (adon) in the adc control/sta- tus register. a delay time is then required for the converter to stabilize (typically 10 m s, see electrical characteristics)). when the a/d function is enabled, the associated pins (see mcu block diagram) may be used as analog inputs. the inputs must first be enabled for analog input by setting the corresponding bit(s) of the relevant port configuration register as de- scribed in the section on i/o ports. bits ch2 to ch0 of the a/d converter control/status register may then be coded to select the channel to be converted. using a pin, or pins, as analog inputs does not affect the ability to read the port as logic inputs. the a/d converter may be disabled by resetting the adon bit. this feature allows the reduction of power consumption when no conversion is in progress. the a/d converter is disabled after pow- er-on and external resets. when enabled, the a/d converter performs a con- tinuous conversion of the selected channel. when a conversion is completed (16 m s for f cpu =4 mhz), the result is loaded into the read only result data register and the coco (conversion com- plete) flag is set. no interrupt is generated. any write to the a/d converter control/status register aborts the current conversion, resets the coco flag and starts a new conversion. the a/d converter is ratiometric. an input voltage equal to, or greater than v dd , converts to ffh (full scale) without overflow indication if greater. an in- put voltage equal to, or lower than v ss converts to 00h. the conversion is monotonic: the results nev- er decrease if the analog input does not and never increase if the analog input does not. the 8-bit conversion is accurate to within 2 lsb. the minimal conversion time is 32 adc clock cy- cles (16 m s if a/d clock frequency at 2 mhz). the a/d converter clock is generated from the cpu clock divided by 2. the high and low level reference voltages are con- nected to v dd and v ss . conversion accuracy may therefore be degraded by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. the a/d converter is not affected by wait mode but, in power sensitive applications, it can be disa- bled before entering this mode. when the mcu enters halt mode with the a/d converter ena- bled, the a/d clocks are stopped and the converter is disabled until the halt mode is exited and the start-up delay has elapsed. a stabilisation time is also required before accurate conversions can be performed.
65/117 ST7285C 4.6.3 register description a/d control/status register (csr) address: 0071h e read/write reset value: 00 h b7: coco conversion complete. coco is set as soon as a new conversion can be read from the result data register. coco is cleared by reading the result or writing to the a/d converter control/status register. b6: reserved, must be programmed to 0 b5: adon a/d converter on . adon allows the a/d converter to be switched on and off in order to reduce consumption when needed. when turned on (adon = 1), a delay time (typically 10 m s) is necessary for the adc to stabi- lize. conversions may be inaccurate during this period. b4 - b3: reserved, must be programmed to 0. b2-0: ch2-ch0 channel selection these bits select the analog input to convert, 000 selecting ain0 and 111 selecting ain7 (fewer than 8 lines may be available, depending on device specifications: see block diagram). a/d data register (dr) address: 0070h e read only reset value: (undefined) b7-0: ad7-ad0 analog converted value . this register contains the converted analog value in the range 00h to 0ffh 70 coco 0 adon 0 0 ch2 ch1 ch0 70 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0
66/117 ST7285C 4.7 rds filter the radio data system (rds) filter peripheral consists of a switched capacitor (sc) bandpass filter centered on 57 khz. this filter selects the rds components from the multiplex radio signal. the filter output is directly used by the demodula- tor. the comparator limits the signal to digital lev- els. the comparator output feeds the rds demod- ulator. 4.7.1 features 57khz switched capacitor (sc) bandpass filter comparator d/a converter for comparator offset compensa- tion by software power down mode. figure 32. rds filter block diagram rw fisel phi1 adr reset rdsref register interface test mode selector d/a converte r (offset-compensation) comparator rdscomp stop clkin (4.332mhz) rdsfil tm2tm smoothing filter prefilter (anti- buffer 8th order sc filter aliasing) mpx to demodulator 10 m f 270p f
67/117 ST7285C rds filter ( cont'd) 4.7.2 functional description the rds filter is of classical switched capacitor type, comprising: an anti-aliasing filter, the sc-fil- ter proper and a smoothing filter connected in cas- cade. the block diagram is given infigure 33. the filter peripheral is composed of the following functional blocks: prefilter . the anti-aliasing filter consists of a 2 nd order sallen-key filter. the phase response in the passband is linear. the cut-off frequency is located at about 360khz. the prefilter includes an operational amplifier with a gain of 80 db. sc filter . the sc filter is a 8 th order bandpass filter. it comprises 4 cascaded biquads. the bi- quads all have the same scheme and differ only in their capacitor values. the switches are con- trolled by a clock generator which produces non- overlapping clock phases. buffer . the output of the sc-filter cannot be connected to resistive loads, since this would se- verely reduce its gain. a buffer is therefore con- nected between the sc filter and the smoothing filter. smoothing filter . the smoothing filter connect- ed to the sc-filter (through the buffer) is a simple rc low pass filter. the output is connected to rdsfil pin (external connection) and to the comparator. comparator . the comparator is connected to the smoothing filter and is able to detect zero- crossing in less than 125ns. the digital output of the comparator is connected via a port to the rds demodulator. d/a converter . a maximum offset of 1mv is al- lowed on the comparator's inputs. the offset compensation is achieved as follows: in a software selectable test mode, the input of the filter is switched to rdsref (=2.5v). the d/ a converter register (rdsfi1) is set to zero and then incremented by software until the compara- tor changes its sign. test mode selector . this function is controlled via 4 bits in the filter control register (rds fi2). it selects the various test modes. (see next point). st7 interface registers. these are described below. rds fi1 address 005ah: e read/write register b7 = reserved. b6 = comp comparator output (read only). b5-0 = ad5-ad0 offset correction value output by d/a (1lsb=2mv). rds fi2 address 005bh e read/write register b7-5 = reserved. b4 = pdb power down bit (1 = run; 0 = power-down) b3-0 = tm3-tm0 mode select. only modes shown in the table below are valid; other modes are reserved. when the internal filter is switched off, the rds- comp pin can be used as an input and to feed the demodulator from an external filter. 76 543210 - comp ad5 ad4 ad3 ad2 ad1 ad0 7 6 543210 - - - pdb tm3 tm2 tm1 tm0 tm3 tm2 tm1 tm0 mode 0000 filter off (reset state) 0011 normal operating mode 1101 offset compensation mode
68/117 ST7285C 4.8 rds demodulator the rds demodulator is a fully digital radio data system demodulator. the module includes 57khz carrier recovery, rds clock (1187.5hz) recovery, bi-phase decoder, fast ari indicator and signal quality indicator. the module is controlled through st7 registers. the rds signal is fed in through the pin rdscomp. the reference frequency is de- rived from the st7 quartz oscillator. therefore, the quartz frequency must be 8.664mhz. 4.8.1 features pure digital rds demodulator without external components. phase polarity data extractor. phase integral data extractor. data extractor selectable: a) automatically via quality detector; b) via software. selectable quality indicator: a) rds signal quality; b) polarity difference and integral data. selectable time constant for 57khz pll. selectable inhibit of pll regulation to be used for af tests and temporary field strength weakness (i.e. tunnels or other obstacles to radio recep- tion). fast ari indicator, controlled by software. figure 33. rds demodulator block diagram 0 1 0 1 0 1 rdscomp arp aren lock upr qen lck1 lck0 57khz pll fast ari indicator apolarityo bi-phase decoder aintegralo bi-phase decoder differential decoder 1 dat1 differential decoder 2 dat2 sdat rds dat qual2 quality detector qual1 lck3 lck2 squal rds clock quality 1187.5hz bit pll
69/117 ST7285C rds demodulator (cont'd) 4.8.2 functional description the rds demodulator is fed with a 57khz band- pass filtered and limited multiplex signal. it contains the following functional blocks: 57khz pl l. this circuit is implemented as a var- iable counter controlled by a acostaso phase comparator. to achieve fast lockup time, the low- pass filter features four software selectable time constants. following a reset, the longest time constant is selected and used for the locked con- dition. the time constant relates to the time needed to compensate a 90 degree phase devi- ation. as the pll locks to 0 and 180 degrees, whatever is closest, this is the maximum possible phase deviation. the selectable time constants are listed in the following register description. 1187.5hz pll . this circuit detects zero cross- ings of the phase of the input signal. after low pass filtering, this information is used to control a variable divider, which generates the rds clock. the time constant of the low pass filter is also se- lectable in four steps. the regulation of both plls may be inhibited by software. this may be used to afreezeo the actual phase relation in order to bridge a certain time of weak or non-existing input signal. (e.g. during af tests, breakdown in field strength,...). depending of the precision of the quartz oscillator some sec- onds of weak input signal may be spanned with- out loosing the lock condition. apolarityo phase decoder . with the help o the recovered 57khz carrier, the sign of the input sig- nal phase is integrated over one bit (48 sam- ples). aintegralo phase decoder . the relative phase angle of the input signal to the recovered carrier is measured. again 48 samples are accumulat- ed. regarding of the apolarity phase decoder, this system is less sensitive to the precision of the recovered carrier, but is more sensitive with respect to ignition spikes. differential decoder . every phase decoder out- put is fed into its own differential decoder. for er- ror correction purposes, a quality bit can be generated in order to mark all differences be- tween the two decoder outputs. quality detector . this unit measures the amount of opposite phase samples. with an error free sig- nal; every bit consists of 24 positive and 24 neg- ative phase samples related to the carrier. due to noise, this balance may be disturbed. all bits with a relation greater than 40 to 8 are marked as bad. this quality information may be used by the soft- ware for an improved error correction. it also may be used internally (selection by software) to switch automatically between apolarityo and ainte- gralo phase decoders. the source of rds data may be one or the other output of these two decoders. the source of the quality output may be selected from the quality detector or from the exor which builds the difference between the two differential decoders. ari indicator . in order to receive a correct rds signal, the57khz pll regulation mustbe changed in accordance with the presence of ari. therefore a fast ari indicator is implemented. this function may be optionally taken over by software. interface registers . these allow control of the demodulator circuit by the mcu. register de- scriptions are given below:
70/117 ST7285C rds demodulator (cont'd) rds de1 address 005c h reset value: 0000 0000b b7 = lock inhibits regulation of plls to keep the current phase value during weak signal conditions. 0: normal regulation (reset value) 1: inhibit regulation. b6-5 = lck3 - lck2 select time constant for 1187.5hz pll. b4-3 = lck1 - lck0 select time constant of 57khz pll. b2 = qen enables automatic selection of input to differential decoder 1. 0 = enable selection by quality (reset value) 1 = disable selection b1 = sdat selects differential decoder for the rds data output. 0 = differential decoder 1 (reset value) 1 = differential decoder 2. b0 = squal selects quality for the quality output. 0 = from the quality detector (qal1) (reset value) 1 = exclusive or of differential decoders (qal2). rds de2 e address 005d h reset value: 0xxx xxxx b b7 = upr software reset to various demodulator parts. 0 = normal run mode (reset value) 1 = demodulator reset. after wring this bit to one, a reset pulse will be gen- erated. the bit will then be automatically reset to zero. this bit is always read as a zero. b6 = qal output of the quality detector which is actually de- tected. this bit is fed into the rds-gbs module. b5 = qal1 output of the quality detector. b4 = qal2 resulant of xor of dat1 and dat2. b3 = dat rds-dat output which is actually detected. this bit is fed into the rds-gbs module. b2 = dat1 output of the phase polarity data extractor. b1 = dat2 output of the phase integral data extractor. b0 = clk rds clock output (1187.5hz) 7 654321 0 lock lck3 lck2 lck1 lck0 qen sdat squal lck3 lck2 lock time needed for max (90 ) deviation 0 0 160ms (reset value) 0 1 80ms 1 0 40ms 1 1 20ms lck1 lck0 lock time needed for max (90 ) deviation 0 0 16ms(reset value) 0 1 8ms 1 0 4ms 1 1 2ms 70 upr qal qal1 qal2 dat dat1 dat2 clk
71/117 ST7285C rds demodulator (cont'd) rds de3 e address 005e h reset value: xxxx x000b b7-3 = reserved. b2 = ari ari indicator. 0 = pure rds, no ari (reset value) 1 = rds plus ari. note that this bit is simply an indicator. b1 = aren selects software or hardware ari indication. 0 = internally by hardware (reset value) 1 = forced by software according to arp bit. b0 = arp preset ari indication. 0 = ari (reset value) 1 = pure rds without ari. rds de4 e address 005f h reset value: 0xx0 0000b b7 = detm selects test mode when set to a1o. this bit must be kept in the reset state (a0o) for normal operation. b6-5 = reserved. b4-1 = te4-te1 reserved. these bits are for internal test use only: they must be kept in the reset state (all a0o) for normal operation b0 = ndepor enables the module 0 = module disabled (reset value) 1 = module enabled (normal operating mode). 70 - - - - - ari aren arp 70 detm - - te4 te3 te2 te1 nde- por
72/117 ST7285C 4.9 rds g.b.s 4.9.1 introduction the main task of the gbs module is to acquire group and block synchronization of a received rds data steam, which is provided in a modified shortened cyclic code. in order to achieve synchronization, a syndrome is calculated on every data clock pulse. detection of a valid syndrome is indicated by flag vsi with as- sociated interrupt, while the corresponding block is kept in bl(0:2). starting in bit_sync mode the sw can use cna zero count interrupt (cna=1) and vsi check for synchronization phase. if the synchronization criteria is fulfilled, the sw can switch to blk_sync mode, setting counter cna to 26 and cnb to the current block code. the sw maintains block synchronization easily by check- ing vsi and ord, which indicates a correct block order. an optional grp_sync mode can be entered for rds standby operation using the appropriate counter interrupt selection. the combination of software triggered syndrome calculation, a second 26-bit shift register and a 26- bit quality register, allow highly flexible error cor- rection by software. single quality errors, representing a 1 or 2 bit rdsdat error, are indicated by the sqe flag. they can be corrected by sw with high security. 4.9.2 features hardware implemented decoding of rds data stream. hardware triggered syndrome calculation with every rising edge of rdsclk. storage of 26 rds bits (1 block). fast syndrome calculation (within 2.4 m satf osc =8.664mhz). 5-bits rds-counter cna and 2-bit rds-block counter cnb. selectable counter interrupt for bit/block/ group-sync mode. avalid syndromeo detection unit with interrupt and block code output. selectable mmbs radio paging option for block e syndrome detection. avalid block ordero flag. extended aerror correction by softwareo support. software triggered syndrome calculation. parallel storage of 26 rdsdat bits and 26 quality bits for high flexibility. single/multiple quality-error flags. figure 34. principles of baseband coding block1 block2 block3 block4 group = 4 blocks = 104 bits m 15 m 14 m 13 m 12 m 11 m 10 m 9 m 8 m 7 m 6 m 5 m 4 m 3 m 2 m 1 m 0 c 9 ' c 8 ' c 7 ' c 6 ' c 5 ' c 4 ' c 3 ' c 2 ' c 1 ' c 0 ' block = 26bits information word = 16-bits check word = 10-bits
73/117 ST7285C rds g.b.s. (cont'd) figure 35. g.b.s. block diagram address decoder st7 interface addresses timing generator addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 addr0 addr1 addr2 addr3 26-bit quality register qr0...qr3 26-bit rdsdat register dr0...dr3 26-bit shift register sr0...sr3 10-bit polynomial shift sy0...sy1 syndrome detection & block coder block order 5-bit count register cna 2-bit count register cnb 2 2 10 irq vse cni rdsclk cnaz cnbz ord vsi vsi nckpoly clkshift sin sin addr4 addr5 addr4 addr4 addr6 fosc(8.664mhz) itsync phi1(4.332mhz) a[3:0] nsyncsel r/w reset d[7:0] data clock clock nclock clock sin rdsdat rdsclk qual register circuit bl[2:0] compare circuit autoreload
74/117 ST7285C rds g.b.s. (cont'd) 4.9.3 functional description 4.9.3.1 principles of baseband coding figure 34 illustrates the principles of baseband coding. the largest element in the structure is called a agroupo. each group contains 4 blocks of 26 bits each. each block contains an information word (16 bits) and a check-word (10bits). the basic baseband data rate e is 1187.5 bits/s. the baseband is a modified shortened cyclic code, that means the transmitted vector c(x) is given by: c(x) = d(x) +m(x) * x 10 + {m(x) * x 10 }/d(x) | mod g(x) where, m(x) represents the 16-bit message vector: m(x) = m 15* x 15 +m 14* x 14 +...+ m 1* x 1 +m 0* x 0 g(x) represents the polynomial generator: g(x) = x 10 +x 8 +x 7 +x 5 +x 4 +x 3 +1 and d(x) represents the offset word according to the values tabulated in table 9 below. for more information about the theory and imple- mentation of the modified shortened cyclic code, please refer to the specification of the european broadcasting union. 4.9.3.2 hardware configuration the gbs circuit comprises the following functional blocks; these are shown schematically in the block diagram, figure 35. 26-bit shift register (sr3- sr0), may act, either as a straight 26-bit delay or as a recirculating shift register. on each rising edge of rdsclk a new rds-bit is shifted into the register. then, the con- tents of the shift register are rotated 26 times (one circuit) for syndrome calculation. in error correction mode (ecm=1), the shift reg- ister acts only as a circular register. new rds-bits are not shifted in. they are stored in the parallel shift register dr0- dr3. polynomial division circuit, comprising a 10-bit shift register (sy0- sy1) with feedback taps for syndrome calculation. during the rotation of the shift register the rds-bits are passed serially into the polynomial division register where the syndrome is calculated and stored. syndrome detection circuit, compares the cal- culated syndrome with a 5(6)-word syndrome rom. the output consists of the block code bl[2:0] and the vsi flag with its associated inter- rupt. vsi is high when a valid syndrome is detect- ed. detection of offset syndrome, e, is enabled by control bit us. 5-bit counter (cna), counts down on every rising edge of rdsclk. the counter reload register can be written by software. on zero count, it restarts immediately with the value of the reload register and can generate an interrupt on zero count. this counter is used as rds-bit counter (26...1). 2-bit counter (cnb), counts down on every zero count of cna. the counter can be written by soft- ware. cnb is running free and can generate an interrupt. this counter is used as rds-block counter (3...1) timing generator block comprising a modulo- 28 counter with end stops and some combina- tional logic. the modulo-28 counter is used to generate one shift clock, 26 rotate clocks and one end of calculation clock. in error correction mode (ecm=1) the shift clock is masked. 26-bit rdsdat register (dr3-dr0), in parallel to shift register sr3-sr1. it works in straight shift mode only. on each rising edge of the rdsclk the rdsdat-bit is shifted into the register. this register is used for temporary block storage dur- ing error correction. 26-bit quality register (qr3-qr0), works in straight shift mode only. on each rising edge of the rdsclk the quality bit coming from the demodulator is shifted into the register. table 9. offset words and their corresponding syndromes offset (block) block code bl 2 bl 1 bl 0 offset word d 9 ,d 8 ,d 7 ,...,d 0 syndrome d 9 ,d 8 ,d 7 ,...,d 0 a 0 1 0 0011111100 1111011000 b 0 0 1 0110011000 1111010100 c 1 0 0 0101101000 1001011100 c' 0 0 0 1101010000 1111001100 d 0 1 1 0110110100 1001011000 e 1 0 1 0000000000 0000000000 wrong 1 1 1 all others all others
75/117 ST7285C rds g.b.s. (cont'd) 4.9.3.3 gbs registers sixteen registers are dedicated to interfacing the group and block synchronization module to the cpu. these registers, together with their symbolic names, bit names and address are presented in tabular form in table 10 below and are here de- scribed in greater detail. register reset states: all registers bits are set to a0o during reset, except for cna4-cna0, cnb1, cnb0 and ord, which are set to a1o. srx - shift registers b7,6 = sr0: contain the 2 last transmitted bits c1',c0' of the checkword. b5-0 are not used and are always read as a0o. b7-0 = sr1: contain the 8 first transmitted bits (c9'...c2') of the checkword. b7-0 = sr2: contain the 8 last information bits (m7'...m0') of the message vector. b7-0 = sr3: contain the 8 first information bits (m15'...m8') of the message vector. sy0 - polynomial register 0 b7,6 = sy0: contain the 2 least significant bits of the calculated syndrome. for valid syndromes, these two bits are a0. b5 is not used, and is always read as a0o. b4 = us (usa option). setting us to a1o enables detection of block e. b3 = ord flag. set to a1o when block counter cb[1:0] is equal to block code bl[1:0]: otherwise it is a0o. stable with vsi or cni. read only. reset value is one. b2-0 = bl[2:0] block code, see table 9. stable with cni or vsi. read only. sy1 - polynomial register 1 b7-0 = sy1: contain the 8 most significant bits (p9'...p2') of the calculated syndrome. table 10. gbs register map register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sr0 - shift reg. 0 0060h c 1 'c 0 '------ sr1 - shift reg. 1 0061h c 9 'c 8 'c 7 'c 6 'c 5 'c 4 'c 3 'c 2 ' sr2 - shift reg. 2 0062h m 7 m 6 m 5 m 4 m 3 m 2 m 1 m 0 sr3 - shift reg. 3 0063h m 15 m 14 m 13 m 12 m 11 m 10 m 9 m 8 sy0 - polynomial reg. 0 0064h p 1 p 0 - us ord bl2 bl1 bl0 sy1 - polynomial reg. 1 0065h p 9 p 8 p 7 p 6 p 5 p 4 p 3 p 2 gs_cnt - count reg. 0066h cnb1 cnb0 sync cna4 cna3 cna2 cna1 cna0 gs_int - interrupt reg. 0067h cal car ecm vsi vse cni ce1 ce0 dr0 - rdsdat reg. 0 0068h dr1 dr0 - mqe sqe qal rcl rda dr1 - rdsdat reg. 1 0069h dr9 dr8 dr7 dr6 dr5 dr4 dr3 dr2 dr2 - rdsdat reg. 2 006ah dr17 dr16 dr15 dr14 dr13 dr12 dr11 dr10 dr3 - rdsdat reg. 3 006bh dr25 dr24 dr23 dr22 dr21 dr20 dr19 dr18 qr0 - quality reg. 0 006ch qr1 qr0 - - - - - - qr1 - quality reg. 1 006dh qr9 qr8 qr7 qr6 qr5 qr4 qr3 qr2 qr2 - quality reg. 2 006eh qr17 qr16 qr15 qr14 qr13 qr12 qr11 qr10 qr3 - quality reg. 3 006fh qr25 qr24 qr23 qr22 qr21 qr20 qr19 qr18
76/117 ST7285C rds g.b.s. (cont'd) gs_cnt - count register b7-6 = cnb[1;0] free-running 2-bit counter ; used as block/order counter. it is decremented on zero- count of cna[4:0]. the zero-counts of cna and cnb are used for counter interrupt generation. re- set value equals one. b5 = sync: set to a1o whenever cna[4;0] reach- es a zero-count. it is valid for one period of rdsclk. read only. sync flag is used when a counter interrupt is desired on every rdsclk (used for general timing or ari filter service), while the blk-sync interrupt service is performed eve- ry 26 bits (cna=26). b4-0 = cna[4:0]: 5-bit r/w autoreload counter; used as rds bit counter . it is decremented on every rising edge of rdsclk. when writing to cna, both a latch and the counter itself are writ- ten. immediately after reaching zero-count, the contents of the latch are loaded back into the counter (autoreload), so the zero-count state can never be read by software. the zero-count of cna is used for counter interrupt generation. reset val- ue equals one. gs_int - interrupt register b7 = cal : start calculation. writing a a1o into cal leads to a new syndrome calculation. cal is al- ways read as a0o. used in software error correc- tion. b6 = car: calculation running . set to a1o by writ- ing cal=1. it returns to a0o when the syndrome calculation is complete (vsi valid). read only. used in software error correction. b5 = ecm: error correction mode. if error correc- tion by software is to be performed, ecm must be set to a1o. this suppresses both shift and rotate clocks for shift registers sr3-sr0, making them available for software-triggered syndrome calcula- tions which may require more than one rdsclk period. on completion of a correction, ecm must be reset to a0o and the current status of sr3-sr0 must be retrieved from the shadow registers dr3- dr0 by a copy routine. b4 = vsi: valid syndrome interrupt . this flag is set to a1o when the block code (bl[2:0]) is equal to one of the six valid syndromes. otherwise, it is reset to a0o. vsi is valid on completion of a syndrome cal- culation, for one period of rdsclk. however, vsi must be reset by software at the end of the inter- rupt service routine. vsi and cni interrupts are ored to the active-high level interrupt, itsync. b3 = vse: valid syndrome interrupt enable. set- ting vse to a1o enables the vsi interrupt. b2 = cni : counter interrupt . this flag is set to a1oon the zero-count of cna/cnb or on the rising edge of rdsclk, depending on the setting of cne[1:0]. cni is valid on completion of the syn- drome calculation, for one period of rdsclk. however, cni must be reset by software at the end of the interrupt service routine. vsi and cni interrupts are ored to the active high level inter- rupt itsync. b1,0 = cne[1:0] . enables and selects the counter interrupt, see table 11 below: table 11. counter interrupt source selection dr0 - rdsdat register 0 b7,6 = dr[1:0] . receives rdsdat sequence. b5 = reserved, always read as a0o. b4 = mqe: multiple quality error . set to a1o when 2 or more low quality bit are detected during the last block (26 bits). mqe is valid for one period of rdsclk, starting with cna zero-count and is re- set by hardware at the end of this period. b3 = sqe: single quality error . set to a1o when a low quality bit is detected during the last block (26 bits). sqe is valid for one period of rdsclk, starting with cna zero-count and is reset by hard- ware at the end of this period. b2 = qal . transparent quality input signal from rds demodulator; read only. b1 = rcl . transparent rdsclk input signal from rds demodulator; read only. b0 = rda . transparent rdsdat input signal from rds demodulator; read only. drx - rds data registers dr1. b7-0 contain bits 9-2 of a received rdsdat sequence. dr2. b7-0 contain bits 17-10 of a received rds- dat sequence. dr3. b7-0 contain bits 18-25 of a received rds- dat sequence. cne1 cne0 counter interrupt source selection 0 0 counter interrupt disabled 01 counter interrupt on every rising edge of rdsclk 10 counter interrupt on cna zero-count state 11 counter interrupt on cna & cnb zero count states
77/117 ST7285C rds g.b.s. (cont'd) qr0 - quality register b7-6 = qr[1:0] receives quality sequence. b5-0 = reserved; always read as a0o. qrx - quality registers qr1. b7-0 contain bits 9-2 of a received quality sequence. qr2. b7-0 contain bits 17-10 of a received qual- ity sequence. qr3. b7-0 contain bits 25-18 of a received qual- ity sequence. 4.9.4 acquisition of group and block synchronization new group and block synchronization is neces- sary after switching on the receiver, on tuning to a new station, or after a prolonged signal fade. the syndrome is calculated for every single received rds-data bit. all valid syndromes corresponding to offset words a to e are shown intable 9. blocks within each group are identified by offset words a, b, c or c', and d. this fact is used for block and group synchronization. detection and coding of block e is enabled by control bit us in polynomial register 0. block e is used for addi- tional radio paging information in north america. for detailed information, see united states rdbs standard specification, published by nrsc. 4.9.5 application tips it is recommended not to load cna with a0o, be- cause this would generate a cna zero-count inter- rupt after every syndrome calculation, initiated ei- ther by positive edge of rdsclk or by writing a a1o to cal. all data and flags are derived from the positive edge of rdsclk and thus are only valid for one period of this clock. all interrupt service routines (vsi or cni inter- rupts) must be completed before the next positive edge of rdsclk (i.e. within 842ms), except when error correction mode is selected (ecm=1). in this case, the interrupt service may take up to 21.9ms in block_sync mode. 4.9.6 block synchronization software there are many strategies to achieve rds block synchronization, a standard method with a simpli- fied synchronization criteria is briefly described. the software starts in bit-sync mode. cna is loaded with a1o and the counter interrupt is ena- bled on cna zero-count. on each interrupt, the syndrome is checked via the vsi flag until vsi is a1o. then the blockcode bl[2:0] and the cna count are saved; the software continues until the next valid syndrome detection. if bit distance (26) and block order are correct, the rds block synchronization is achieved, and the software can switch to block_sync mode. the software can easily maintain block synchroniza- tion by checking the vsi and ord flags, the latter indicates correct block order. this method does not respect dummy syndromes (valid syndromes appearing between two valid blocks). an optional grp_sync mode may be entered for rds standby operation, using the appropriate counter interrupt selection. 4.9.7 error correction software software triggered syndrome calculation, a sec- ond 26-bit shift register and a 26-bit quality regis- ter, allow highly flexible error correction by soft- ware, using the quality signal information from the rds demodulator. a quality alowo state indicates an uncertain corre- sponding rdsdat bit. because of the differential decoding of rdsdat, not only the rdsdat bit pointed to by quality, but also the following rds- dat bit may be wrong. thus a single quality error can represent a single or a double data bit error. a single quality error within one block is indicated by the sqe flag, multiple quality errors within one block are indicated by the mqe flag. the software starts error correction by setting ecm to a1o, to make the main shift registers sr3- sr0 available for software triggered syndrome calculations, which may take longer than one peri- od of rdsclk (842ms). new incoming rdsdat-bits are stored in the par- allel shift registers dr3-dr0. moreover, the cur- rent contents of the quality registers qr3-qr0, must be saved in ram, in order to be used for the following error correction. error correction may be performed by reversing the rdsdat bits in shift registers sr3-sr0, which are indicated as bad in the quality register (with respect to rdsdat differential decoding). after each reverse, a new syndrome calculation is started (cal=1) and checked (vsi). single quality errors, representing a 1 or 2 bit rdsdat error may be corrected with high security. on completion of the correction, the contents of dr3-dr0 must be copied back into shift registers sr3-sr0, and ecm must be set to a0o.
78/117 ST7285C 5 software 5.1 st7 architecture the 8-bit st7 core is designed for high code effi- ciency. it contains 6 internal registers, 17 main ad- dressing modes and 63 instructions. the 6 internal registers include 2 index registers, an accumula- tor, a 16-bit program counter, a stack pointer and a condition code register. the two index registers x and y enable indexed addressing modes with or without offset, along with read-modify-write type data manipulations. these registers simplify branching routines and data modifications. the 16-bit program counter is able to address up to 64k of rom /eprom memory. the 6-bit stack pointer provides access to a 64-level stack and an upgrade to an 8-bit stack pointer is foreseen in or- der to be able to manage a 256-level stack. the core also includes a condition code register pro- viding 5 condition flags that indicate the result of the last instruction executed. the 17 main addressing modes, including indirect relative and indexed addressing, allow sophisti- cated branching routines or case-type functions. the indexed indirect addressing mode, for in- stance, permits look-up tables to be located any- where in the address space, thus enabling very flexible programming and compact c-based code. the 63-instruction instruction set is 8-bit oriented with a 2-byte average instruction size. this in- struction set offers, in addition to standard data movement and logic/arithmetic functions, byte multiplication, bit manipulation, data transfer be- tween stack and accumulator (push/pop) with di- rect stack access, as well as data transfer using the x and y registers. 5.2 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in 7 main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two sub-modes called long and short: the long addressing mode is the most powerful because it can reach any byte in the 64kb ad- dressing space, but the instruction is bigger and slower than the short addressing mode. the short addressing mode is less powerful be- cause it can generally only access page zero (0000 - 00ffh range), but the instruction size is more compact, and faster. all memory to memo- ry instructions are only working with short ad- dressing modes (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) both modes have pros and cons, but the program- mer does not need to choose which one is the best: the st7 assembler will always choose the best one. addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5
79/117 ST7285C st7 addressing modes (cont'd) table 12. st7 addressing mode overview: mode syntax destination ptr addr ptr size lngth inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc+/-127 + 1 relative indirect jrne [$10] pc+/-127 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3
80/117 ST7285C st7 addressing modes (cont'd) inherent: all related instructions are single byte ones. the op-code fully specify all required information for the cpu to process the operation. these instruc- tions are single byte ones.: immediate: the required data byte to do the operation is fol- lowing the op-code. these are two byte instruc- tions, one for the op-code and the other one for the immediate data byte. direct (short, long): the data byte required to carry out the operation is found by its memory address, which follows the op-code. the direct addressing mode consists of two sub- modes: direct (short): the address is a byte, thus require only one byte after the op-code, but only allow 00 - ff address- ing space. direct (long): the address is a word, thus allowing 64kb ad- dressing space, but requires 2 bytes after the op- code. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low pow- er mode) halt halt oscillator (lowest pow- er mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations available long and short direct instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- stractions operations bcp bit compare short direct instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump operations sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine
81/117 ST7285C st7 addressing modes (cont'd) indexed (no offset, short, long) the required data byte to do the operation is found by its memory address, which is defined by the un- signed addition of an index register (x or y) with an offset which follows the op-code. the indirect addressing mode consists of three sub-modes: indexed (no offset): there is no offset, (no extra byte after the op- code), but only allows 00 - ff addressing space. indexed (short): the offset is a byte, thus require only one byte af- ter the op-code, but only allow 00 - 1fe address- ing space. indexed (long): the offset is a word, thus allowing 64kb address- ing space, but requires 2 bytes after the op-code. indirect (short, long): the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the op-code. the indi- rect addressing mode consists of two sub-modes: indirect (short): the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the op-code. indirect (long): the pointer address is a byte, the pointer size is a word, thus allowing 64kb addressing space, and requires 1 byte after the op-code. no offset, long and short indexed instruc. function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- stractions operations bcp bit compare no offset and short indexed inst. only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump operations sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine available long and short indirect instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- stractions operations bcp bit compare short indirect instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump operations sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine
82/117 ST7285C st7 addressing modes (cont'd) indirect indexed (short, long): this is a combination of indirect and short indexed addressing mode. the required data byte to do the operation is found by its memory address, which is defined by the unsigned addition of an index regis- ter value (x or y) with a pointer value located in memory. the pointer address follows the op-code. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short): the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the op-code. indirect indexed (long): the pointer address is a byte, the pointer size is a word, thus allowing 64kb addressing space, and requires 1 byte after the op-code. relative mode (direct, indirect): this addressing mode is used to modify the pc register value, by adding an 8 bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct): the offset is following the op-code. relative (indirect): the offset is defined in memory, which address follows the op-code. long and short indirect indexed instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- stractions operations bcp bit compare short indirect indexed instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate opera- tions swap swap nibbles call, jp call or jump subroutine available relative direct/indirect instructions function jrxx conditional jump callr call relative
83/117 ST7285C 5.3 st7 instruction set the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 main groups as illustrated in the following table: using a pre-byte the instructions are described with one to four op- codes. in order to extend the number of available op- codes for an 8-bit cpu (256 op-codes), three dif- ferent prebyte opcodes are defined. these preb- ytes modify the meaning of the instruction they precede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc op-code pc+1 additional word (0 to 2) according to the number of bytes required to compute the effective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90replace an x based instruction using im- mediate, direct, indexed, or inherent ad- dressing mode by a y one. pix 92 replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding in- direct addressing mode. it also changes an instruction using x in- dexed addressing mode to an instruction using indirect x indexed addressing mode. piy 91 replace an instruction using x indirect in- dexed addressing mode by a y one. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret code condition flag modification sim rim scf rcf
84/117 ST7285C mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine return pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if port b int pin = 1 (no port b interrupts) jril jump if port b int pin = 0 (port b interrupt) jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > jrule jump if (c + z = 1) unsigned <=
85/117 ST7285C ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m hinzc pop cc cc m push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= a <= c reg, m n z c rrc rotate right true c c => a => c reg, m n z c rsp reset stack pointer s = max allowed sbc substract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= a <= 0 reg, m n z c sll shift left logic c <= a <= 0 reg, m n z c srl shift right logic 0 => a => c reg, m 0 z c sra shift right arithmetic a7 => a => c reg, m n z c sub substraction a = a - m a m n z c swap swap nibbles a7-a4 <=> a3-a0 reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z mnemo description function/example dst src h i n z c
86/117 ST7285C 6 electrical characteristics 6.1 absolute maximum ratings devices of the st72 family contain circuitry to pro- tect the inputs against damage due to high static voltage or electric fields. nevertheless, it is recom- mended that normal precautions be observed in order to avoid subjecting this high-impedance cir- cuit to voltages above those quoted in the abso- lute maximum ratings. for proper operation, it is recommended that v in and v out be constrained within the range: v ss v in and v out v dd to enhance reliability of operation, it is recom- mended to configure unused i/os as inputs and to connect them to an appropriate logic voltage level such as v ss or v dd . all the voltage in the following tables are refer- enced to v ss . stresses above those listed as aabsolute maxi- mum ratingso may cause permanent damage to the device. functional operation of the device at these conditions is not implied. exposure to maxi- mum rating conditions for extended periods may affect device reliability. absolute maximum ratings (voltage referenced to v ss ) symbol ratings value unit v dd /v dda /v ddp supply voltage 0.3 to +6 v |v dda - v dd | supply voltage < 50 mv v in input voltage v ss - 0.3 to v dd + 0.3 v i v dd -i v ss total current into v dd /v ss pins 50/20 ma i current drain per pin excluding v dd and v ss 20 ma t a maximum operating temperature range t l to t h -40to +85 c t stg storage temperature range -65 to +150 c v hv high voltage on pins ph3, ph4, ph5 10 v
87/117 ST7285C 6.2 power considerations the average chip-junction temperature, t j , in de- grees celsius, may be calculated using the follow- ing equation: t j =t a +(p d x q j a )(1) where: t a is the ambient temperature in c, q j a is the package junction-to-ambient thermal resistance, in c/w, p d is the sum of p int and p i/o , p int is the product of i dd and v dd , expressed in watts. this is the chip internal power p i/o represents the power dissipation on input and output pins; user determined. for most applications p i/o

88/117 ST7285C 6.3 dc electrical characteristics (t a = -40 to +85 c unless otherwise specified) note: all voltages are referred to v ss unless otherwise specified. note :at85 c and v dd = 5.5v, code 255 is missing. note *) : the 3rd harmonic (57khz) must be less than -40db with respect to the input signal plus gain standard i/o port pins symbol parameter conditions min typ max unit v il input low level voltage - - 0.3xv dd v v ih input high level voltage 0.7xv dd --v v ol output low level voltage i=-5ma - - 0.5 v i=-1.6ma - - 0.3 v v ol output low level voltage on pins ph3, ph4, ph5 i=-5ma - - 1.0 v i=-1.6ma - - 0.4 v v oh output high level voltage i=5ma 3.1 - - v i=1.6ma 3.4 - - v i l input leakage current v ss 89/117 ST7285C 6.4 ac electrical characteristics (t a = -40 to +85 c unless otherwise specified) 6.5 control timing (operating conditions t a = -40 to +85 c unless otherwise specified) note: 1. the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 cycles. symbol parameter condition s value unit min typ. max v dd operating supply voltage 4.332 mhz internal 4.5 5.5 v i dd supply current run mode f ext = 8.664mhz v dd = 5.0v, f int = 4.332mhz wait mode f ext = 8.664mhz v dd = 5.5v, f int = 4.332mhz halt mode, v dd = 5.0v 3 200 20 5 320 ma ma m a v rm data retention mode halt mode 2 v symbol parameter conditi ons value unit min typ. max f osc frequency of operation v dd = 4.5v f external f internal 8.664 4.332 mhz t ilch halt mode recovery startup time crystal resonator 20 ms t rl external reset input pulse width 1.5 t cyc t porl power reset duration 4096 t cyc t dogl watchdog reset output pulse width 200 ns t dog watchdog time-out 12,288 786,432 t cyc t ilil interrupt pulse period (1) t cyc t oxov crystal oscillator start-up time 50 ms t ddr power up rise time v dd min 100 ms
90/117 ST7285C control timing (cont'd) serial peripheral interface symbol ref. characteristics f osc = 8.0mhz unit min. max. operating frequency =f osc/2 =f op f op (m) master dc 0.5 f op f op (s) slave dc 4.0 mhz 1 cycle time t cyc(m) master 2.0 t cyc t cyc(s) slave 240 ns 2 enable lead time ns t lead(m) master (1) t lead(s) slave 120 3 enable lag time ns master (1) slave 120 4 clock (sck)high time t w(sckh) master 100 ns t w(sckh) slave 90 ns 5 clock (sck) low time t w(sckl) master 100 ns t w(sckl) slave 90 ns 6 data set-up time t su(m) master 100 ns t su(s) slave 100 ns 7 data hold time (inputs) t h(m) master 100 ns t h(s) slave 100 ns t a 8 access time (time to data active from high impedance state) ns slave 0 120 t dis 9 disable time (hold time to high impedance state) ns slave 240 10 data valid t v(m) master (before capture edge) 0.25 t cyc(m) t v(s) slave (after enable edge) (2) 120 ns 11 data hold time (outputs) t ho(m) master (before capture edge) 0.25 t cyc(m) t ho(s) slave (after enable edge) 0 ns 12 rise time (20% v dd to 70% v dd ,c l = 200pf) t rm spi outputs (sck, mosi, miso) 100 ns t rs spi inputs (sck, mosi, miso, ss) 2.0 m s 13 fall time (70% v dd to 20% v dd ,c l t fm spi outputs (sck, mosi, miso) 100 ns t fs spi inputs (sck, mosi, miso, ss) 2.0 m s
91/117 ST7285C control timing (cont'd) figure 36. spi master timing diagram cpol=0, cpha=1 note : measurement points are v ol ,v oh ,v il and v ih figure 37. spi master timing diagram cpol=1, cpha+1 note : measurement points are v ol ,v oh ,v il and v ih 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 5 4 vr000107 d7-in d6-in d0-in d7-out d6-out d0-out 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 4 5 vr000108 d7-out d6-out d0-out d7-in d6-in d0-in
92/117 ST7285C control timing (cont'd) figure 38. spi master timing diagram cpol=0, cpha=0 note : measurement points are v ol ,v oh ,v il and v ih figure 39. spi master timing diagram cpol=1, cpha=1 note: measurement points are v ol ,v oh ,v il and v ih 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 45 vr000109 d7-out d6-out d0-out d7-in d6-in d0-in 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 4 5 vr000110 d7-out d6-out d0-out d7-in d6-in d0-in
93/117 ST7285C control timing (cont'd) figure 40. spi slave timing diagram cpol=0, cpha=1 note: measurement points are v ol ,v oh ,v il and v ih figure 41. spi slave timing diagram cpol=1, cpha=1 note: measurement points are v ol ,v oh ,v il and v ih 1 67 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z vr000111 d7-out d6-out d0-out d7-in d6-in d0-in 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 54 (input) 2 3 8 9 high-z vr000112 d7-out d6-out d0-out d7-in d6-in d0-in
94/117 ST7285C control timing (cont'd) figure 42. spi slave timing diagram cpol=0, cpha=0 figure 43. spi slave timing diagram cpol=1, cpha=0 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z vr000113 d7-in d6-in d0-in d7-out d6-out d0-out 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z vr000114 d7-in d6-in d0-in d7-out d6-out d0-out
95/117 ST7285C control timing (cont'd) 1. the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of the falling edge of scl 2. the maximum hold time of the start condition only has to be met if the interface does not stretch the low period of scl signal cb = total capacitance of one bus line in pf figure 44. definition of timing terminology i 2 c bus interface parameter standard i 2 c fast i 2 c symbol unit min max min max bus free time between a stop and start condition 4.7 1.3 tubs m s hold time start condition. after this period, the first clock pulse is generated 4.0 0.6 thd:sta m s low period of the scl clock 4.7 1.3 tlow m s high period of the scl clock 4.0 0.6 thigh m s set-up time for a repeated start condition 4.7 0.6 tsu:sta m s data hold time 0 (1) 0 (1) 0.9(2) thd:dat m s data set-up time 250 100 tsu:dat ns rise time of both sda and scl signals 1000 20+0.1cb 300 tr ns fall time of both sda and scl signals 300 20+0.1cb 300 tf ns set-up time for stop condition 4.0 0.6 tsu:sto ns capacitive load for each bus line 400 400 cb pf tbuf tlow tr tf thd:sta tsp thd:sta thigh thd:dat tsu:dat tsu:sta tsu:sto sda scl
96/117 ST7285C 7 general information 7.1 package mechanical data figure 45. 80-pin plastic quad flat package table 14. ordering information table note: for this device, sgs-thomson can only receive motorola s19 format for rom codes. pqfp080 dim mm inches min typ max min typ max a 3.40 0.134 a1 0.25 0.010 a2 2.55 2.80 3.05 0.100 0.110 0.120 b 0.30 0.45 0.012 0.018 c 0.13 0.23 0.005 0.009 d 22.95 23.20 23.45 0.904 0.913 0.923 d1 19.90 20.00 20.10 0.783 0.787 0.791 d3 18.40 0.724 e 16.95 17.20 17.45 0.667 0.677 0.687 e1 13.90 14.00 14.10 0.547 0.551 0.555 e3 12.00 0.472 e 0.80 0.031 k 0 7 l 0.65 0.80 0.95 0.026 0.031 0.037 l1 1.60 0.063 number of pins n80 nd24ne16 sales types rom size ram size temperature range package st 7285a5cq5 48k 3k -20 to +70 c qfp80 st 7285a5cq6 48k 3k -40 to +85 c qfp80 st 7285a5cq8 48k 3k -25 to +85 c qfp80
november 1997 97/117 r rev. 1.0 st72e85 st72t85 8-bit mcu for rds with 48k eprom/otp, 3k ram, adc, two timers, spi, i 2 c and sci interfaces n 4.5v to 5.5v supply operating range n operation at 8.664mhz oscillator frequency for rds compatibility n fully static operation n -40 cto+85 c maximum operating temperature range n run, wait, slow, halt, and ram retention modes n user eprom/otp: 48 kbytes n data ram: 3 kbytes, including 128 byte stack n 80 pin plastic package n 62 multifunctional bidirectional i/o lines: programmable interrupt inputs on some i/os 8 analog inputs emi filtering n two 16-bit timers, each featuring: 2 input captures 2 output compares external clock input (on timer a) pwm and pulse generator modes n rds radio data system filter, demodulator and gbs circuits n 8-bit analog-to-digital converter with 8 channel analog multiplexer n digital watchdog n dual spi serial peripheral interface n sci serial communications interface n full i 2 c multiple master/ slave interface n 2khz beep signal generator n master reset and power-on reset n 8-bit data manipulation n 63 basic instructions n 17 main addressing modes n 8 x 8 unsigned multiply instruction n true bit manipulation n complete development support on pc/dos/ windows tm real-time emulator n full software package (c-compiler, cross- assembler, debugger) cqfp80-w pqfp80
98/117 st72e85 st72t85 1 general description 1.1 introduction the st72e85 is the eprom version of the ST7285C. please refer to the ST7285C rom de- vice datasheet for further details. from the user's point of view, both thest72e85 and the ST7285C possess the same software and hardware features. an additional mode is available to allow program- ming of the eprom user memory array. this is set by a specific voltage source applied to the v pp / test pin. the st72e85 (eprom) features a 48k eprom memory. watchdog activation is available by software for eprom and otp devices. figure 1. st72e85 block diagram *note: eprom and otp versions only. power on reset pa0 - pa7 pin 65..72 pb0 - pb7 pin 73..80 oscin oscout reset v pp / test osc 8 -bit core alu vr01735p internal clock address and data bus timer a port a port b a/d converter 8 4 spi b port c pc0 - pc7 pin 5..12 spi a port d i 2 c sci 8 ram 3k rds filter,demod,gbs 8 8 8 timer b 4 4 2 pd0 - pd7 pin 13..20 2 port e pe0 - pe7 pin 25..32 8 port f pf0 - pf7 pin 33..40 8 port h port g ph0 - ph5 pin 53..58 6 pg0 - pg7 pin 45..52 8 rom or eprom* 48k watchdog rdscomp mpx rds fil rds ref ars aint v dd v ss v ddp v ssp v dda v ssa 2 2
99/117 st72e85 st72t85 1.2 pin description all i/os from port a to port d, as well as ph0, 1 and 2, feature alternate function compatibility. software selectable input pull-ups are available on ports featuring interrupt capability (pc4, pc5, pd4, pd5, pf0-pf3, pg3). vssa vdda mpx rdsref rdsfil rdscomp ph5 ph4 ph3 ph2/rdsdata ph1/rdsclkout ph0/rdsqual pg7 pg6 pg5 pg4 pg3 pg2 pg1 pg0 ars aint vddp vssp vssp vddp oscout oscin pc0/miso_b pc1/mosi_b pc2/sck_b pc3/ss_b pc4/oc2_b pc5/oc1_b pc6/ic2_b pc7/ic1_b pd0/miso_a pd1/mosi_a pd2/sck_a pd3/ss_a pd4 pd5 pd6/scl pd7/sda reset vpp*/test vdd vss 1 2 3 4 5 6 7 8 9 (i10) 10 (i10) 11 12 13 14 15 16 17 (i9) 18 (i9) 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 (i1) 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 29 30 31 32 37 38 39 40 pb7/beep/ clkout pb6/clkext pb5/oc2_a pb4/oc1_a pb3/ic2_a pb2/ic1_a pb1/rdi pb0/tdo pa7/ain7 pa6/ain6 pa5/ain5 pa4/ain4 pa3/ain3 pa2/ain2 pa1/ain1 pa0/ain0 pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 33 34 35 36 *) on eprom/otp versions only (i2)(i2)(i2)(i2)
100/117 st72e85 st72t85 pin pin name(s) basic function alternate function remarks 1v ssp ground for output buffers - this pin is connected to pin 41 2v ddp power supply for output buffers this pin is connected to pin 42 3 oscout oscillator output pin. 4 oscin oscillator input pin. 5 pc0/miso_b i/o port pc0 spi b master in/slave out data input/output alternate function or i/o. the i/o configuration is software selectable as triggered input or push pull output. 6 pc1/mosi_b i/o port pc1 spi b master out/ slave in data input/ output 7 pc2/sck_b i/o port pc2 spi b serial clock 8 pc3/ss_b i/o port pc3 spi b slave select 9 pc4/oc2_b i/o port pc4 output compare 2 on timer b alternate function or i/o. software selectable as triggered input, push pull output, or triggered interrupt input with pull up (interrupt i10). 10 pc5/oc1_b i/o port pc5 output compare 1 on timer b 11 pc6/ic2_b i/o port pc6 input capture 2 on timer b alternate function or i/o. the i/o configuration is software selectable as triggered input or push pull output. 12 pc7/ic1_b i/o port pc7 input capture 1 on timer b. 13 pd0/miso_a i/o port pd0 spi a master in/ slave out data input/ output 14 pd1/mosi_a i/o port pd1 spi a master out/ slave in data input/ output 15 pd2/sck_a i/o port pd2 spi a serial clock 16 pd3/ss_a i/o port pd3 spi a slave select 17 pd4 i/o port pd4 - software selectable as triggered input, push pull output, open drain output or triggered inter- rupt input with pull up (interrupt i9). 18 pd5 i/o port pd5 - 19 pd6/scl i/o port pd6 i 2 c serial clock alternate function or i/o. the i/o configuration is software selectable as triggered input or open drain output. 20 pd7/sda i/o port pd7 i 2 c serial data 21 reset general reset - bidirectional. an active low signal forces mcu initialization. this event is the top priority non- maskable interrupt. as an output, it can be used to reset external peripherals. 22 v pp /test reserved - input. this pin must be tied directly to v ss dur- ing normal operation. in programming mode, this pin is connected to v pp . 23 v dd power supply for all logic circuitry - except for output buffers and pull-ups. 24 v ss ground for all logic circuitry -
101/117 st72e85 st72t85 25 pe0 i/o port pe0 - software selectable as triggered input or push pull output. 26 pe1 i/o port pe1 - 27 pe2 i/o port pe2 - 28 pe3 i/o port pe3 - 29 pe4 i/o port pe4 - 30 pe5 i/o port pe5 - 31 pe6 i/o port pe6 - 32 pe7 i/o port pe7 - 33 pf0 i/o port pf0 - software selectable as triggered input, a push pull output, open drain output, or triggered inter- rupt input with pull up (interrupt i2). 34 pf1 i/o port pf1 - 35 pf2 i/o port pf2 - 36 pf3 i/o port pf3 - 37 pf4 i/o port pf4 - software selectable as a triggered input or as a push pull output. 38 pf5 i/o port pf5 - 39 pf6 i/o port pf6 - 40 pf7 i/o port pf7 - 41 v ssp ground for output buffers. - this pin is connected to pin 1. 42 v ddp power supply for output buffers - this pin is connected to pin 2. 43 aint reserved - must be tied to 5v 44 ars reserved - must be tied to 5v 45 pg0 i/o port pg0 - software selectable as triggered input or push pull output. 46 pg1 i/o port pg1 - 47 pg2 i/o port pg2 - 48 pg3 i/o port pg3 - software selectable as triggered input, a push pull output, open drain output, or triggered inter- rupt input with pull up (interrupt i1). 49 pg4 i/o port pg4 - software selectable as triggered input or push pull output. note that ph0, 1, 2 offer alternate function capabilities for test purposes. 50 pg5 i/o port pg5 - 51 pg6 i/o port pg6 - 52 pg7 i/o port pg7 - 53 ph0/ rdsqual i/o port ph0 rds quality signal 54 ph1/ rdsclk- out i/o port ph1 rds gbs clock out signal 55 ph2/ rdsdata i/o port ph2 rds gbs data sig- nal 56 ph3 i/o port ph3 - software selectable as triggered input or high voltage (10v max) open drain output. 57 ph4 i/o port ph4 - 58 ph5 i/o port ph5 - 59 rdscomp rds comp input sig- nal used to feed the demodulator from an external filter when the internal filter is switched off. 60 rdsfil rds filtered output signal used for demodulator test purposes. 61 rdsref rds input reference 62 mpx rds input signal 63 v dda analog power supply for rds and adc circuits 64 v ssa analog ground pin pin name(s) basic function alternate function remarks
102/117 st72e85 st72t85 65 pa0/ain0 i/o port pa0 analog input to adc alternate function or i/o. the i/o configuration is software selectable as triggered input or push pull output. note that when a pin is used as an- alog input it must not be configured as an out- put to avoid conflicts with the analog voltage to be measured. 66 pa1/ain1 i/o port pa1 67 pa2/ain2 i/o port pa2 68 pa3/ain3 i/o port pa3 69 pa4/ain4 i/o port pa4 70 pa5/ain5 i/o port pa5 71 pa6/ain6 i/o port pa6 72 pa7/ain7 i/o port pa7 73 pb0/tdo i/o port pb0 sci transmit data out alternate function or i/o. the i/o configuration is software selectable as triggered input or push pull output. 74 pb1/rdi i/o port pb1 sci receive data in 75 pb2/ic1_a i/o port pb2 input capture 1 on timer a 76 pb3/ic2_a i/o port pb3 input capture 2 on timer a 77 pb4/oc1_a i/o port pb4 output compare 1 on timer a 78 pb5/oc2_a i/o port pb5 output compare 2 on timer a 79 pb6/clkext i/o port pb6 external clock on timer a 80 pb7/beep/ clkout i/o port pb7 beep or cpu clock. this pin can be a push pull output delivering the beep signal (2khz) or the cpu clock, accord- ing to the miscellaneous register settings. pin pin name(s) basic function alternate function remarks
103/117 st72e85 st72t85 1.3 memory map table 1. memory map address block register name reset status remarks 0000h 0001h 0002h 0003h port a data reg data direction reg not used not used 00h 00h r/w register r/w register absent absent 0004h 0005h 0006h 0007h port b data reg data direction reg not used not used 00h 00h r/w register r/w register absent absent 0008h 0009h 000ah 000bh port c data reg data direction reg option reg not used 00h 00h --00----b r/w register r/w register r/w register absent 000ch 000dh 000eh 000fh port d data reg data direction reg option reg not used 00h 00h --00----b r/w register r/w register r/w register absent 0010h 0011h 0012h 0013h port e data reg data direction reg not used not used 00h 00h r/w register r/w register absent absent 0014h 0015h 0016h 0017h port f data reg data direction reg option reg not used 00h 00h ----0000b r/w register r/w register r/w register absent 0018h 0019h 001ah 001bh port g data reg data direction reg option reg not used 00h 00h ----0---b r/w register r/w register r/w register absent 001ch 001dh 001eh 001fh port h data reg data direction reg not used not used 00h 00h r/w register r/w register absent absent 0020h miscellaneous register 00h see register description 0021h 0022h 0023h spi a data i/o reg control reg status reg xxh 0xh 00h r/w register r/w register read only register 0024h wdg watchdog register 7fh see register description 0025h 0026h 0027h spi b data i/o reg control reg status reg xxh 0xh 00h r/w register r/w register read only register
104/117 st72e85 st72t85 0028h 0029h 002ah 002bh 002ch 002dh 002eh i 2 c cr: control register sr1: status register 1 sr2: status register 2 ccr: clock control register oar1: own address register 1 oar2: own address register 2 dr: data register 00h 00h 00h 00h 00h 00h 00h r/w register read only register read only register r/w register r/w register r/w register r/w register 002fh 0030h reserved 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh timer a control reg2 control reg1 status reg input capture1 high register input capture1 low register output compare1 high register output compare1 low register counter high register counter low register alternate counter high register alternate counter low register input capture2 high register input capture2 low register output compare2 high register output compare2 low register 00h 00h xxh xxh xxh xxh xxh ffh fch 00h 00h xxh xxh xxh xxh r/w register r/w register read only register read only register read only register r/w register r/w register read only register read only register read only register read only register read only register read only register r/w register r/w register 0040h reserved 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh 004eh 004fh timer b control reg2 control reg1 status reg input capture1 high register input capture1 low register output compare1 high register output compare1 low register counter high register counter low register alternate counter high register alternate counter low register input capture2 high register input capture2 low register output compare2 high register output compare2 low register 00h 00h xxh xxh xxh xxh xxh ffh fch 00h 00h xxh xxh xxh xxh r/w register r/w register read only register read only register read only register r/w register r/w register read only register read only register read only register read only register read only register read only register r/w register r/w register 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h sci sci prescaler scsr: status register scdr: data register scbrr: baud rate register sccr1: control register 1 sccr2: control register 2 pscbrr: receive baud rate reg reserved pscbrt: transmit baud rate reg 1100000xb xxh 00x----xb xxh 00h 00h --- 00h read only register r/w register r/w register r/w register r/w register r/w register reserved st use r/w register 0058h reserved 0059h reserved 005ah 005bh rds filter rds fi1 rds fi2 r/w register r/w register address block register name reset status remarks
105/117 st72e85 st72t85 1.4 eprom erasure st72e85 eprom devices are erased by expo- sure to high intensity uv light admitted through the transparent window. this exposure discharges the floating gate to its initial state through induced photo current. it is recommended that the st72e85 devices be kept out of direct sunlight, since the uv content of sunlight can be sufficient to cause functional fail- ure. extended exposure to room level fluorescent lighting may also cause erasure. an opaque coating (paint, tape, label, etc...) should be placed over the package window if the product is to be operated under these lighting con- ditions. covering the window also reduces i dd in power-saving modes due to photo-diode leakage currents. an ultraviolet source of wave length 2537 ? yield- ing a total integrated dosage of 15 watt-sec/cm is required to erase the st72e85. the device will be erased in 15 to 20 minutes if such a uv lamp with a 12mw/cm power rating is placed 1 inch from the device window without any interposed filters. 005ch 005dh 005eh 005fh rds demodulator rds de1 rds de2 rds de3 rds de4 see register description 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh 006ch 006dh 006eh 006fh rds gbs sr0 -shift reg 0 sr1 -shift reg 1 sr2 -shift reg 2 sr3 -shift reg 3 sy0 -polynomial reg 0 sy1 -polynomial reg 1 gs_cnt count reg gs_int interrupt reg dr0 -rdsdat reg 0 dr1 -rdsdat reg 1 dr2 -rdsdat reg 2 dr3 -rdsdat reg 3 qr0 -quality reg 0 qr1 -quality reg 1 qr2 -quality reg 2 qr3 -quality reg 3 see register description 0070h 0071h adc data reg control/status reg xxh 00h read only register read/write register 0072h to 007fh reserved 0080h to 0bffh 0c00h to 0c7fh ram 3k bytes of which stack 128 bytes user variables and subroutine nesting 0c80h to 3fffh reserved 4000h to ffdfh otp/eprom 48k bytes (49120 bytes) user application code and data ffe0h to ffff h user vectors interrupt and reset vectors address block register name reset status remarks
106/117 st72e85 st72t85 1.5 eprom/rom i c compatibility application note in order to insure full compatibility between the eprom and the rom versions of the st7285 mi- crocontroller, certain timing conditions have to be respected when using the i 2 c interface. otherwise the i 2 c interface of the st72e85 can: detect an unexpected start or stop condi- tion with bus error detection generate unexpected btf flag settings unexpected start or stop condition detec- tion in the st72e85 device, due to the synchronisation between the i 2 c peripheral and the f cpu (4.332mhz), an unexpected start or stop con- dition can be detected in slave mode. this gener- ates an unexpected bus error and sets the berr bit in the sr2 register. to avoid this effect, the following i c timing has to be respected: tsu dat >1/f cpu ~ 230,84ns thd dat >1/f cpu ~ 230,84ns in the rom version of the st7285, the i 2 c periph- eral and f cpu are asynchronous, so no unexpect- ed start or stop condition can be detected. unexpected btf flag setting after a stop con- dition due to the reason described in the previous para- graph, the btf flag can be set unexpectedly in the i 2 c interface of the st72e85 after a stop condi- tion is detected in slave mode. to recover from this condition, reset and subse- quently set the pe bit in the cr register when the stopf and btf flags are set at the same time af- ter a stop condition detection. the i 2 c interface is not subject to this effect in the rom version of the st7285. figure 46. i c timing diagram sda scl tsu dat thd dat data bit start bit
107/117 st72e85 st72t85 2 electrical characteristics 2.1 absolute maximum ratings devices of the st72 family contain circuitry to pro- tect the inputs against damage due to high static voltage or electric fields. nevertheless, it is recom- mended that normal precautions be observed in order to avoid subjecting this high-impedance cir- cuit to voltages above those quoted in the abso- lute maximum ratings. for proper operation, it is recommended that v in and v out be constrained within the range: v ss v in and v out v dd to enhance reliability of operation, it is recom- mended to configure unused i/os as inputs and to connect them to an appropriate logic voltage level such as v ss or v dd . all the voltage in the following tables are refer- enced to v ss . stresses above those listed as aabsolute maxi- mum ratingso may cause permanent damage to the device. functional operation of the device at these conditions is not implied. exposure to maxi- mum rating conditions for extended periods may affect device reliability. absolute maximum ratings (voltage referenced to v ss ) symbol ratings value unit v dd /v dda /v ddp supply voltage 0.3 to +6 v |v dda - v dd | supply voltage < 50 mv v in input voltage v ss - 0.3 to v dd + 0.3 v i v dd -i v ss total current into v dd /v ss pins 50/20 ma i current drain per pin excluding v dd and v ss 20 ma t a maximum operating tempera- ture range t l to t h -40to +85 c t stg storage temperature range -65 to +150 c v hv high voltage on pins ph3, ph4, ph5 10 v esd esd sensitivity on ph5 (pin 58) 1.5 kv lu lu sensitivity on mpx (pin 62) class d
108/117 st72e85 st72t85 2.2 power considerations the average chip-junction temperature, t j , in de- grees celsius, may be calculated using the follow- ing equation: t j =t a +(p d x q j a )(1) where: t a is the ambient temperature in c, q j a is the package junction-to-ambient thermal resistance, in c/w, p d is the sum of p int and p i/o , p int is the product of i dd and v dd , expressed in watts. this is the chip internal power p i/o represents the power dissipation on input and output pins; user determined. for most applications p i/o

109/117 st72e85 st72t85 2.3 dc electrical characteristics (t a = -40 to +85 c unless otherwise specified) note: all voltages are referred to v ss unless otherwise specified. note :at85 c and v dd = 5.5v, code 255 is missing. note *) : the 3rd harmonic (57khz) must be less than -40db with respect to the input signal plus gain general symbol parameter condition s min typ. max unit v dd supply voltage rds filter operational 4.5 5.5 v without rds filter capability 3.0 6.0 standard i/o port pins symbol parameter conditions min typ max unit v il input low level voltage - - 0.3xv dd v v ih input high level voltage 0.7xv dd --v v ol output low level voltage i=-5ma - - 0.5 v i=-1.6ma - - 0.3 v v ol output low level voltage on pins ph3, ph4, ph5 i=-5ma - - 1.0 v i=-1.6ma - - 0.4 v v oh output high level voltage i=5ma 3.1 - - v i=1.6ma 3.4 - - v i l input leakage current v ss 110/117 st72e85 st72t85 2.4 ac electrical characteristics (t a = -40 to +85 c unless otherwise specified) 2.5 control timing (operating conditions t a = -40 to +85 c unless otherwise specified) note: 1. the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 cycles. symbol parameter conditions value unit min typ. max v dd operating supply voltage 4.332 mhz internal 4.5 5.5 v i dd supply current run mode f ext = 8.664mhz v dd = 5.0v, f int = 4.332mhz wait mode f ext = 8.664mhz v dd = 5.5v, f int = 4.332mhz halt mode, v dd =5.0v 3 tbd 20 5 ma ma m a v rm data retention mode halt mode 2 v symbol parameter test condition s value unit min typ. max f osc frequency of operation v dd = 4.5v f external f internal 8.664 4.332 mhz t ilch halt mode recovery startup time crystal resonator 20 ms t rl external reset input pulse width 1.5 t cyc t porl power reset duration 4096 t cyc t dogl watchdog reset output pulse width 200 ns t dog watchdog time-out 12,288 786,432 t cyc t ilil interrupt pulse period (1) t cyc t oxov crystal oscillator start-up time 50 ms t ddr power up rise time v dd min 100 ms
111/117 st72e85 st72t85 control timing (cont'd) serial peripheral interface symbol num. characteristics f osc = 8.0mhz unit min. max. operating frequency =f osc/2 =f op f op (m) master dc 0.5 f op f op (s) slave dc 4.0 mhz 1 cycle time t cyc(m) master 2.0 t cyc t cyc(s) slave 240 ns 2 enable lead time ns t lead(m) master (1) t lead(s) slave 120 3 enable lag time ns master (1) slave 120 4 clock (sck)high time t w(sckh) master 100 ns t w(sckh) slave 90 ns 5 clock (sck) low time t w(sckl) master 100 ns t w(sckl) slave 90 ns 6 data set-up time t su(m) master 100 ns t su(s) slave 100 ns 7 data hold time (inputs) t h(m) master 100 ns t h(s) slave 100 ns t a 8 access time (time to data active from high impedance state) ns slave 0 120 t dis 9 disable time (hold time to high impedance state) ns slave 240 10 data valid t v(m) master (before capture edge) 0.25 t cyc(m) t v(s) slave (after enable edge) (2) 120 ns 11 data hold time (outputs) t ho(m) master (before capture edge) 0.25 t cyc(m) t ho(s) slave (after enable edge) 0 ns 12 rise time (20% v dd to 70% v dd ,c l = 200pf) t rm spi outputs (sck, mosi, miso) 100 ns t rs spi inputs (sck, mosi, miso, ss) 2.0 m s 13 fall time (70% v dd to 20% v dd ,c l t fm spi outputs (sck, mosi, miso) 100 ns t fs spi inputs (sck, mosi, miso, ss) 2.0 m s
112/117 st72e85 st72t85 control timing (cont'd) figure 2. spi master timing diagram cpol=0, cpha=1 note : measurement points are v ol ,v oh ,v il and v ih figure 3. spi master timing diagram cpol=1, cpha+1 note : measurement points are v ol ,v oh ,v il and v ih 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 5 4 vr000107 d7-in d6-in d0-in d7-out d6-out d0-out 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 4 5 vr000108 d7-out d6-out d0-out d7-in d6-in d0-in
113/117 st72e85 st72t85 control timing (cont'd) figure 4. spi master timing diagram cpol=0, cpha=0 note : measurement points are v ol ,v oh ,v il and v ih figure 5. spi master timing diagram cpol=1, cpha=1 note: measurement points are v ol ,v oh ,v il and v ih 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 45 vr000109 d7-out d6-out d0-out d7-in d6-in d0-in 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 4 5 vr000110 d7-out d6-out d0-out d7-in d6-in d0-in
114/117 st72e85 st72t85 control timing (cont'd) figure 6. spi slave timing diagram cpol=0, cpha=1 note: measurement points are v ol ,v oh ,v il and v ih figure 7. spi slave timing diagram cpol=1, cpha=1 note: measurement points are v ol ,v oh ,v il and v ih 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z vr000111 d7-out d6-out d0-out d7-in d6-in d0-in 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 54 (input) 2 3 8 9 high-z vr000112 d7-out d6-out d0-out d7-in d6-in d0-in
115/117 st72e85 st72t85 control timing (cont'd) figure 8. spi slave timing diagram cpol=0, cpha=0 figure 9. spi slave timing diagram cpol=1, cpha=0 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z vr000113 d7-in d6-in d0-in d7-out d6-out d0-out 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z vr000114 d7-in d6-in d0-in d7-out d6-out d0-out
116/117 st72e85 st72t85 control timing (cont'd) 1. the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of the falling edge of scl 2. the maximum hold time of the start condition only has to be met if the interface does not stretch the low period of scl signal cb = total capacitance of one bus line in pf figure 10. definition of timing terminology i 2 c bus interface parameter standard i 2 c fast i 2 c symbol unit min max min max bus free time between a stop and start condition 4.7 1.3 tubs m s hold time start condition. after this period, the first clock pulse is generated 4.0 0.6 thd:sta m s low period of the scl clock 4.7 1.3 tlow m s high period of the scl clock 4.0 0.6 thigh m s set-up time for a repeated start condition 4.7 0.6 tsu:sta m s data hold time 0 (1) 0 (1) 0.9(2) thd:dat m s data set-up time 250 100 tsu:dat ns rise time of both sda and scl signals 1000 20+0.1cb 300 tr ns fall time of both sda and scl signals 300 20+0.1cb 300 tf ns set-up time for stop condition 4.0 0.6 tsu:sto ns capacitive load for each bus line 400 400 cb pf tbuf tlow tr tf thd:sta tsp thd:sta thigh thd:dat tsu:dat tsu:sta tsu:sto sda scl
117/117 st72e85 st72t85 3 general information 3.1 package mechanical data figure 47. 80-pin ceramic quad flat package table 15. ordering information table information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-tho mson microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of sgs-tho mson microelectronics. ? 1997 sgs-thomson microelectronics - all rights reserved. purchase of i 2 c components by sgs-tho mson microelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore spain - sweden - swit zerland - taiwan - thailand - united kingdom - u.s.a. dim mm inches min typ max min typ max a 3.24 0.128 a1 0.20 0.008 b 0.30 0.35 0.45 0.012 0.014 0.018 c 0.13 0.15 0.23 0.005 0.006 0.009 d 23.35 23.90 24.45 0.919 0.941 0.963 d1 19.57 20.00 20.43 0.770 0.787 0.804 d3 18.40 0.724 e 17.35 17.90 18.45 0.683 0.705 0.726 e1 13.61 14.00 14.39 0.536 0.551 0.567 e3 12.00 0.472 e 0.80 0.031 g 13.75 14.00 14.25 0.541 0.551 0.561 g1 19.75 20.00 20.25 0.778 0.787 0.797 g2 1.17 0.046 l 0.35 0.80 0.014 0.031 8.89 0.350 number of pins n80 cqfp080w sales types program memory ram size temperature range package st 72e85a5g0 48k eprom 3k +25 c cqfp80 st 72t85a5q6 48k otp 3k -40 to +85 c pqfp80

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